JP2006108605A - フラッシュメモリ素子のウォール酸化膜形成方法及び素子分離膜形成方法 - Google Patents
フラッシュメモリ素子のウォール酸化膜形成方法及び素子分離膜形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 138
- 238000002955 isolation Methods 0.000 title claims abstract description 24
- 230000003647 oxidation Effects 0.000 claims abstract description 43
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims description 22
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 238000002156 mixing Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000004140 cleaning Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- 238000009279 wet oxidation reaction Methods 0.000 description 3
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】 フラッシュメモリ素子のウォール酸化膜形成方法は、トレンチの形成された半導体基板を提供する段階と、H2とO2の雰囲気でISSG酸化方式によって酸化工程を行って前記トレンチの内側壁にウォール酸化膜を形成する段階とを含む構成としたことを特徴とする。
【選択図】 図4
Description
H2+O2→H2O+O+OH
11…酸化膜
11a…パッド酸化膜
11b…低電圧ゲート酸化膜
11c…高電圧ゲート酸化膜
12…パッド窒化膜
13…DCS−HTO膜
14…SiON膜
15…第1トレンチ
16…スペーサ用絶縁膜
16a…スペーサ
17…第2トレンチ
18…ウォール酸化膜
19…素子分離膜用絶縁膜
Claims (14)
- (a)トレンチの形成された半導体基板を提供する段階と、
(b)H2とO2の雰囲気でISSG酸化方式によって酸化工程を行って前記トレンチの内側壁にウォール酸化膜を形成する段階とを含むフラッシュメモリ素子のウォール酸化膜形成方法。 - 前記ISSG酸化方式は、850℃以上、且つ1000℃以下の温度範囲で行うことを特徴とする請求項1記載のフラッシュメモリ素子のウォール酸化膜形成方法。
- 前記ISSG酸化方式は、1torr以上、且つ10torr以下の圧力で行うことを特徴とする請求項1または請求項2記載のフラッシュメモリ素子のウォール酸化膜形成方法。
- 前記H2とO2の雰囲気は、O2リッチ雰囲気であることを特徴とする請求項1記載のフラッシュメモリ素子のウォール酸化膜形成方法。
- 前記H2とO2の雰囲気における前記O2の混合割合は、33%以上、且つ60%以下であることを特徴とする請求項4記載のフラッシュメモリ素子のウォール酸化膜形成方法。
- 前記H2とO2の雰囲気における前記H2の混合割合は、0.5%以上、且つ33%以下であることを特徴とする請求項4記載のフラッシュメモリ素子のウォール酸化膜形成方法。
- 前記ウォール酸化膜は、15Å以上、且つ30Å以下の厚さに形成されることを特徴とする請求項1記載のフラッシュメモリ素子のウォール酸化膜形成方法。
- (a)パッド酸化膜の形成された半導体基板を提供する段階と、
(b)前記パッド酸化膜上にパッド窒化膜を蒸着する段階と、
(c)前記パッド窒化膜及び前記パッド酸化膜をエッチングすると同時に、前記半導体基板上の一部をリセスさせて第1トレンチを形成する段階と、
(d)前記第1トレンチの内側壁にスペーサを形成する段階と、
(e)H2とO2の雰囲気でISSG酸化方式によって第1酸化工程を行い、前記スペーサを介して露出される前記半導体基板の上部を酸化処理する段階と、
(f)前記第1トレンチよりも深く前記半導体基板をエッチングして第2トレンチを形成する段階と、
(g)H2とO2の雰囲気でISSG酸化方式によって第2酸化工程を行って前記第2トレンチの内側壁にウォール酸化膜を形成する段階と、
(h)前記第2トレンチが埋め込まれるように素子分離膜を形成する段階と、
を含むことを特徴とするフラッシュメモリ素子の素子分離膜形成方法。 - 前記第1及び第2酸化工程は、850℃以上、且つ1000℃以下の温度範囲で行うことを特徴とする請求項8記載のフラッシュメモリ素子の素子分離膜形成方法。
- 前記第1及び第2酸化工程は、1torr以上、且つ10torr以下の圧力で行うことを特徴とする請求項8または請求項9記載のフラッシュメモリ素子の素子分離膜形成方法。
- 前記H2とO2の雰囲気は、O2リッチ雰囲気であることを特徴とする請求項8記載のフラッシュメモリ素子の素子分離膜形成方法。
- 前記H2とO2の雰囲気におけるO2の混合割合は、33%以上、且つ60%以下であることを特徴とする請求項11記載のフラッシュメモリ素子の素子分離膜形成方法。
- 前記H2とO2の雰囲気における前記H2の混合割合は、0.5%以上、且つ33%以下であることを特徴とする請求項11記載のフラッシュメモリ素子の素子分離膜形成方法。
- 前記ウォール酸化膜は、15Å以上、且つ30Å以下の厚さに形成されることを特徴とする請求項8記載のフラッシュメモリ素子の素子分離膜形成方法。
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KR1020040079505A KR100650846B1 (ko) | 2004-10-06 | 2004-10-06 | 플래시 메모리 소자의 소자 분리막 형성방법 |
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JP2006108605A true JP2006108605A (ja) | 2006-04-20 |
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JP2004369027A Pending JP2006108605A (ja) | 2004-10-06 | 2004-12-21 | フラッシュメモリ素子のウォール酸化膜形成方法及び素子分離膜形成方法 |
Country Status (6)
Country | Link |
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US (2) | US7279394B2 (ja) |
JP (1) | JP2006108605A (ja) |
KR (1) | KR100650846B1 (ja) |
CN (1) | CN100403525C (ja) |
DE (1) | DE102004060669A1 (ja) |
TW (1) | TWI293494B (ja) |
Cited By (1)
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JP2010283199A (ja) * | 2009-06-05 | 2010-12-16 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
Families Citing this family (13)
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KR100657088B1 (ko) * | 2004-12-30 | 2006-12-12 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR100629606B1 (ko) * | 2004-12-31 | 2006-09-27 | 동부일렉트로닉스 주식회사 | 고전압 소자 영역의 게이트 산화막 질 개선방법 |
TWI240989B (en) * | 2005-01-17 | 2005-10-01 | Powerchip Semiconductor Corp | Method for forming trench gate dielectric layer |
US20060223267A1 (en) * | 2005-03-31 | 2006-10-05 | Stefan Machill | Method of production of charge-trapping memory devices |
KR100733446B1 (ko) * | 2005-11-16 | 2007-06-29 | 주식회사 하이닉스반도체 | 플라스크형 리세스 게이트를 갖는 반도체 소자의 제조방법 |
KR100799151B1 (ko) * | 2006-06-29 | 2008-01-29 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 소자 분리막 형성방법 |
KR100726093B1 (ko) * | 2006-07-28 | 2007-06-08 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
KR100790296B1 (ko) * | 2006-12-04 | 2008-01-02 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조방법 |
KR100933812B1 (ko) * | 2007-07-02 | 2009-12-24 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
JP4886801B2 (ja) * | 2009-03-02 | 2012-02-29 | 株式会社東芝 | 半導体装置の製造方法 |
CN108122842A (zh) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN109950246A (zh) * | 2017-12-21 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
KR20210094636A (ko) | 2018-12-20 | 2021-07-29 | 어플라이드 머티어리얼스, 인코포레이티드 | 3d nand 애플리케이션들을 위한 메모리 셀 제작 |
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2004
- 2004-10-06 KR KR1020040079505A patent/KR100650846B1/ko not_active IP Right Cessation
- 2004-12-14 TW TW093138677A patent/TWI293494B/zh not_active IP Right Cessation
- 2004-12-15 DE DE102004060669A patent/DE102004060669A1/de not_active Withdrawn
- 2004-12-17 US US11/016,436 patent/US7279394B2/en not_active Expired - Fee Related
- 2004-12-21 JP JP2004369027A patent/JP2006108605A/ja active Pending
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- 2005-05-16 CN CNB2005100726866A patent/CN100403525C/zh not_active Expired - Fee Related
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- 2007-08-02 US US11/833,056 patent/US20080020544A1/en not_active Abandoned
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JP2010283199A (ja) * | 2009-06-05 | 2010-12-16 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
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US7279394B2 (en) | 2007-10-09 |
US20060073661A1 (en) | 2006-04-06 |
DE102004060669A8 (de) | 2006-08-10 |
US20080020544A1 (en) | 2008-01-24 |
TWI293494B (en) | 2008-02-11 |
KR100650846B1 (ko) | 2006-11-27 |
CN1758428A (zh) | 2006-04-12 |
CN100403525C (zh) | 2008-07-16 |
KR20060030651A (ko) | 2006-04-11 |
TW200612514A (en) | 2006-04-16 |
DE102004060669A1 (de) | 2006-04-06 |
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