JP2005521264A5 - - Google Patents

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Publication number
JP2005521264A5
JP2005521264A5 JP2003579285A JP2003579285A JP2005521264A5 JP 2005521264 A5 JP2005521264 A5 JP 2005521264A5 JP 2003579285 A JP2003579285 A JP 2003579285A JP 2003579285 A JP2003579285 A JP 2003579285A JP 2005521264 A5 JP2005521264 A5 JP 2005521264A5
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JP
Japan
Prior art keywords
well
dopant material
type
ion implantation
type dopant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003579285A
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English (en)
Japanese (ja)
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JP2005521264A (ja
JP4361807B2 (ja
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Publication date
Priority claimed from US10/104,939 external-priority patent/US6919236B2/en
Application filed filed Critical
Publication of JP2005521264A publication Critical patent/JP2005521264A/ja
Publication of JP2005521264A5 publication Critical patent/JP2005521264A5/ja
Application granted granted Critical
Publication of JP4361807B2 publication Critical patent/JP4361807B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2003579285A 2002-03-21 2002-12-17 Ｓｏｉデバイス、その製造方法 Expired - Fee Related JP4361807B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/104,939 US6919236B2 (en) 2002-03-21 2002-03-21 Biased, triple-well fully depleted SOI structure, and various methods of making and operating same
PCT/US2002/040398 WO2003081677A1 (en) 2002-03-21 2002-12-17 Based, triple-well fully depleted soi structure, and various methods of making and operating same

Publications (3)

Publication Number Publication Date
JP2005521264A JP2005521264A (ja) 2005-07-14
JP2005521264A5 true JP2005521264A5 (enExample) 2006-08-31
JP4361807B2 JP4361807B2 (ja) 2009-11-11

Family

ID=28040744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003579285A Expired - Fee Related JP4361807B2 (ja) 2002-03-21 2002-12-17 Ｓｏｉデバイス、その製造方法

Country Status (9)

Country Link
US (2) US6919236B2 (enExample)
EP (1) EP1488463B1 (enExample)
JP (1) JP4361807B2 (enExample)
KR (1) KR100939094B1 (enExample)
CN (1) CN100346484C (enExample)
AU (1) AU2002361758A1 (enExample)
DE (1) DE60224847T2 (enExample)
TW (1) TWI270983B (enExample)
WO (1) WO2003081677A1 (enExample)

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US7416927B2 (en) * 2002-03-26 2008-08-26 Infineon Technologies Ag Method for producing an SOI field effect transistor
US7115949B2 (en) * 2002-05-30 2006-10-03 Freescale Semiconductor, Inc. Method of forming a semiconductor device in a semiconductor layer and structure thereof
EP1588418A1 (de) * 2003-01-30 2005-10-26 X-FAB Semiconductor Foundries AG Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur
JP2005116623A (ja) * 2003-10-03 2005-04-28 Nec Electronics Corp 半導体装置およびその製造方法
JP4664631B2 (ja) * 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
TWI240370B (en) * 2004-08-26 2005-09-21 Airoha Tech Corp Substrate structure underlying a pad and pad structure
CN101238580B (zh) * 2005-08-18 2010-06-16 富士通微电子株式会社 半导体器件及其制造方法
JP2007115971A (ja) * 2005-10-21 2007-05-10 Fujitsu Ltd 半導体装置とその製造方法
US7442996B2 (en) * 2006-01-20 2008-10-28 International Business Machines Corporation Structure and method for enhanced triple well latchup robustness
DE102007004859A1 (de) * 2007-01-31 2008-08-14 Advanced Micro Devices, Inc., Sunnyvale SOI-Bauelement mit einer Substratdiode mit Prozess toleranter Konfiguration und Verfahren zur Herstellung des SOI-Bauelements
KR101003115B1 (ko) * 2007-12-12 2010-12-21 주식회사 하이닉스반도체 플로팅 바디 캐패시터를 구비한 반도체 메모리 소자 및 그제조방법
US7843005B2 (en) * 2009-02-11 2010-11-30 International Business Machines Corporation SOI radio frequency switch with reduced signal distortion
US8421156B2 (en) * 2010-06-25 2013-04-16 International Business Machines Corporation FET with self-aligned back gate
FR2980640B1 (fr) * 2011-09-26 2014-05-02 Commissariat Energie Atomique Circuit integre en technologie fdsoi avec partage de caisson et moyens de polarisation des plans de masse de dopage opposes presents dans un meme caisson
CN103489779B (zh) * 2012-06-12 2016-05-11 中国科学院微电子研究所 半导体结构及其制造方法
US9252228B2 (en) 2013-11-29 2016-02-02 Qualcomm Incorporated Threshold voltage adjustment in metal oxide semiconductor field effect transistor with silicon oxynitride polysilicon gate stack on fully depleted silicon-on-insulator
US9257353B1 (en) * 2014-10-24 2016-02-09 GlobalFoundries, Inc. Integrated circuits with test structures including bi-directional protection diodes
FR3038775A1 (fr) 2015-07-09 2017-01-13 St Microelectronics Sa Prise de contact substrat pour un transistor mos dans un substrat soi, en particulier fdsoi
US9621033B2 (en) 2015-09-09 2017-04-11 Nxp Usa, Inc. Charge pump circuit for providing multiplied voltage
US9972395B2 (en) * 2015-10-05 2018-05-15 Silicon Storage Technology, Inc. Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems
US10096708B2 (en) * 2016-03-30 2018-10-09 Stmicroelectronics Sa Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate
FR3053834B1 (fr) * 2016-07-05 2020-06-12 Stmicroelectronics Sa Structure de transistor
US10109620B1 (en) * 2017-07-26 2018-10-23 Globalfoundries Inc. Method for reducing switch on state resistance of switched-capacitor charge pump using self-generated switching back-gate bias voltage
CN109545792B (zh) * 2018-11-29 2022-01-04 上海华力微电子有限公司 一种sonos存储结构及其制造方法
US11444160B2 (en) 2020-12-11 2022-09-13 Globalfoundries U.S. Inc. Integrated circuit (IC) structure with body contact to well with multiple diode junctions
CN113594161B (zh) * 2021-07-30 2024-08-23 锐立平芯微电子(广州)有限责任公司 半导体器件及其制作方法
CN118431316B (zh) * 2024-07-05 2024-10-18 武汉新芯集成电路股份有限公司 半导体器件及其制造方法

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US6677805B2 (en) * 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6661042B2 (en) * 2002-03-11 2003-12-09 Monolithic System Technology, Inc. One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US7432136B2 (en) * 2002-05-06 2008-10-07 Advanced Micro Devices, Inc. Transistors with controllable threshold voltages, and various methods of making and operating same

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