DE60224847T2 - Vorgespannte, total verarmte dreifach-wannen-soi-struktur und verschiedene verfahren zur herstellung und funktion derselben - Google Patents

Vorgespannte, total verarmte dreifach-wannen-soi-struktur und verschiedene verfahren zur herstellung und funktion derselben Download PDF

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Publication number
DE60224847T2
DE60224847T2 DE60224847T DE60224847T DE60224847T2 DE 60224847 T2 DE60224847 T2 DE 60224847T2 DE 60224847 T DE60224847 T DE 60224847T DE 60224847 T DE60224847 T DE 60224847T DE 60224847 T2 DE60224847 T2 DE 60224847T2
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DE
Germany
Prior art keywords
type
doping material
tub
dopant
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60224847T
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German (de)
English (en)
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DE60224847D1 (de
Inventor
Andy C. Wei
Derick J. Bee Caves Wristers
Mark B. Austin Fuselier
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GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE60224847D1 publication Critical patent/DE60224847D1/de
Application granted granted Critical
Publication of DE60224847T2 publication Critical patent/DE60224847T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
DE60224847T 2002-03-21 2002-12-17 Vorgespannte, total verarmte dreifach-wannen-soi-struktur und verschiedene verfahren zur herstellung und funktion derselben Expired - Lifetime DE60224847T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US104939 2002-03-21
US10/104,939 US6919236B2 (en) 2002-03-21 2002-03-21 Biased, triple-well fully depleted SOI structure, and various methods of making and operating same
PCT/US2002/040398 WO2003081677A1 (en) 2002-03-21 2002-12-17 Based, triple-well fully depleted soi structure, and various methods of making and operating same

Publications (2)

Publication Number Publication Date
DE60224847D1 DE60224847D1 (de) 2008-03-13
DE60224847T2 true DE60224847T2 (de) 2009-02-05

Family

ID=28040744

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60224847T Expired - Lifetime DE60224847T2 (de) 2002-03-21 2002-12-17 Vorgespannte, total verarmte dreifach-wannen-soi-struktur und verschiedene verfahren zur herstellung und funktion derselben

Country Status (9)

Country Link
US (2) US6919236B2 (enExample)
EP (1) EP1488463B1 (enExample)
JP (1) JP4361807B2 (enExample)
KR (1) KR100939094B1 (enExample)
CN (1) CN100346484C (enExample)
AU (1) AU2002361758A1 (enExample)
DE (1) DE60224847T2 (enExample)
TW (1) TWI270983B (enExample)
WO (1) WO2003081677A1 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7416927B2 (en) * 2002-03-26 2008-08-26 Infineon Technologies Ag Method for producing an SOI field effect transistor
US7115949B2 (en) * 2002-05-30 2006-10-03 Freescale Semiconductor, Inc. Method of forming a semiconductor device in a semiconductor layer and structure thereof
AU2004208199A1 (en) * 2003-01-30 2004-08-12 X-Fab Semiconductor Foundries Ag SOI structure comprising substrate contacts on both sides of the box, and method for the production of such a structure
JP2005116623A (ja) * 2003-10-03 2005-04-28 Nec Electronics Corp 半導体装置およびその製造方法
JP4664631B2 (ja) * 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
TWI240370B (en) * 2004-08-26 2005-09-21 Airoha Tech Corp Substrate structure underlying a pad and pad structure
CN101238580B (zh) * 2005-08-18 2010-06-16 富士通微电子株式会社 半导体器件及其制造方法
JP2007115971A (ja) * 2005-10-21 2007-05-10 Fujitsu Ltd 半導体装置とその製造方法
US7442996B2 (en) * 2006-01-20 2008-10-28 International Business Machines Corporation Structure and method for enhanced triple well latchup robustness
DE102007004859A1 (de) * 2007-01-31 2008-08-14 Advanced Micro Devices, Inc., Sunnyvale SOI-Bauelement mit einer Substratdiode mit Prozess toleranter Konfiguration und Verfahren zur Herstellung des SOI-Bauelements
KR101003115B1 (ko) * 2007-12-12 2010-12-21 주식회사 하이닉스반도체 플로팅 바디 캐패시터를 구비한 반도체 메모리 소자 및 그제조방법
US7843005B2 (en) * 2009-02-11 2010-11-30 International Business Machines Corporation SOI radio frequency switch with reduced signal distortion
US8421156B2 (en) 2010-06-25 2013-04-16 International Business Machines Corporation FET with self-aligned back gate
FR2980640B1 (fr) * 2011-09-26 2014-05-02 Commissariat Energie Atomique Circuit integre en technologie fdsoi avec partage de caisson et moyens de polarisation des plans de masse de dopage opposes presents dans un meme caisson
CN103489779B (zh) 2012-06-12 2016-05-11 中国科学院微电子研究所 半导体结构及其制造方法
US9252228B2 (en) 2013-11-29 2016-02-02 Qualcomm Incorporated Threshold voltage adjustment in metal oxide semiconductor field effect transistor with silicon oxynitride polysilicon gate stack on fully depleted silicon-on-insulator
US9257353B1 (en) * 2014-10-24 2016-02-09 GlobalFoundries, Inc. Integrated circuits with test structures including bi-directional protection diodes
FR3038775A1 (fr) 2015-07-09 2017-01-13 St Microelectronics Sa Prise de contact substrat pour un transistor mos dans un substrat soi, en particulier fdsoi
US9621033B2 (en) 2015-09-09 2017-04-11 Nxp Usa, Inc. Charge pump circuit for providing multiplied voltage
US9972395B2 (en) * 2015-10-05 2018-05-15 Silicon Storage Technology, Inc. Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems
US10096708B2 (en) * 2016-03-30 2018-10-09 Stmicroelectronics Sa Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate
FR3053834B1 (fr) * 2016-07-05 2020-06-12 Stmicroelectronics Sa Structure de transistor
US10109620B1 (en) * 2017-07-26 2018-10-23 Globalfoundries Inc. Method for reducing switch on state resistance of switched-capacitor charge pump using self-generated switching back-gate bias voltage
CN109545792B (zh) * 2018-11-29 2022-01-04 上海华力微电子有限公司 一种sonos存储结构及其制造方法
US11444160B2 (en) 2020-12-11 2022-09-13 Globalfoundries U.S. Inc. Integrated circuit (IC) structure with body contact to well with multiple diode junctions
CN113594161B (zh) * 2021-07-30 2024-08-23 锐立平芯微电子(广州)有限责任公司 半导体器件及其制作方法
CN118431316B (zh) * 2024-07-05 2024-10-18 武汉新芯集成电路股份有限公司 半导体器件及其制造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920008834A (ko) 1990-10-09 1992-05-28 아이자와 스스무 박막 반도체 장치
US5359219A (en) * 1992-12-04 1994-10-25 Texas Instruments Incorporated Silicon on insulator device comprising improved substrate doping
JP3110262B2 (ja) * 1993-11-15 2000-11-20 松下電器産業株式会社 半導体装置及び半導体装置のオペレーティング方法
JPH0832040A (ja) 1994-07-14 1996-02-02 Nec Corp 半導体装置
JPH0887881A (ja) * 1994-09-19 1996-04-02 Mitsubishi Electric Corp 半導体記憶装置
JPH08153880A (ja) 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
JP3641511B2 (ja) * 1995-06-16 2005-04-20 株式会社ルネサステクノロジ 半導体装置
JP3462301B2 (ja) * 1995-06-16 2003-11-05 三菱電機株式会社 半導体装置及びその製造方法
DE69733603D1 (de) * 1997-01-23 2005-07-28 St Microelectronics Srl NMOS, negative Ladungspumpe
US5923067A (en) 1997-04-04 1999-07-13 International Business Machines Corporation 3-D CMOS-on-SOI ESD structure and method
SG67518A1 (en) * 1997-06-30 1999-09-21 Matsushita Electric Works Ltd Solid-state relay
JP3765163B2 (ja) * 1997-07-14 2006-04-12 ソニー株式会社 レベルシフト回路
US6072217A (en) * 1998-06-11 2000-06-06 Sun Microsystems, Inc. Tunable threshold SOI device using isolated well structure for back gate
US6100567A (en) * 1998-06-11 2000-08-08 Sun Microsystems, Inc. Tunable threshold SOI device using back gate and intrinsic channel region
US6307233B1 (en) * 1998-07-31 2001-10-23 Texas Instruments Incorporated Electrically isolated double gated transistor
KR100302189B1 (ko) * 1999-10-05 2001-11-02 윤종용 에스.오.아이(ｓｏｉ)구조를 갖는 반도체 소자 및 그 제조방법
JP3872927B2 (ja) * 2000-03-22 2007-01-24 株式会社東芝 昇圧回路
US6406948B1 (en) * 2000-07-13 2002-06-18 Chartered Semiconductor Manufacturing Ltd. Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate
JP3475162B2 (ja) * 2000-09-08 2003-12-08 三洋電機株式会社 チャージポンプ回路
US6496055B2 (en) * 2000-12-29 2002-12-17 Intel Corporation Gate enhanced tri-channel positive charge pump
US6677805B2 (en) * 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6661042B2 (en) * 2002-03-11 2003-12-09 Monolithic System Technology, Inc. One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US7432136B2 (en) * 2002-05-06 2008-10-07 Advanced Micro Devices, Inc. Transistors with controllable threshold voltages, and various methods of making and operating same

Also Published As

Publication number Publication date
US7180136B2 (en) 2007-02-20
DE60224847D1 (de) 2008-03-13
AU2002361758A1 (en) 2003-10-08
CN1623238A (zh) 2005-06-01
CN100346484C (zh) 2007-10-31
WO2003081677A1 (en) 2003-10-02
JP4361807B2 (ja) 2009-11-11
KR100939094B1 (ko) 2010-01-28
JP2005521264A (ja) 2005-07-14
US20030178622A1 (en) 2003-09-25
TWI270983B (en) 2007-01-11
TW200307369A (en) 2003-12-01
EP1488463B1 (en) 2008-01-23
US6919236B2 (en) 2005-07-19
KR20040108678A (ko) 2004-12-24
EP1488463A1 (en) 2004-12-22
US20050184341A1 (en) 2005-08-25

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,