JP2005521264A - 偏倚型3ウェル完全空乏soi構造、その製造方法および制御方法 - Google Patents
偏倚型3ウェル完全空乏soi構造、その製造方法および制御方法 Download PDFInfo
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Abstract
一実施形態として、第1型のドーパント材料でドーピングされるバルク基板(30A)と、埋め込み酸化膜(30B)と、活性層(30C)とを含むシリコン・オン・インシュレータ基板(30)上にトランジスタを形成する方法が開示される。当該方法は、前記バルク基板(30A)に第1ウェル領域(50)を形成するために、前記第1型のドーパント材料とは反対の型のドーパント材料を用いて第1イオン注入処理を実行するステップと、前記バルク基板(30A)の前記第1ウェル(50)内に第2ウェル領域(52)を形成するために、前記第1型のドーパント材料と同じ型のドーパント材料を用いて第2イオン注入処理を実行するステップと、前記第1ウェル(50)に電気コンタクト(60)を形成するステップと、前記第2ウェル(60)に電気コンタクトを形成するステップとを含み、前記トランジスタ(32)は前記第2ウェル(52)上の前記活性層(30C)に形成される。当該方法は前記バルク基板(30A)の前記第1ウェル(50)内に形成されるコンタクトウェル(58)をさらに含み、前記コンタクトウェル(58)は前記第2型のドーパント材料と同じ型のドーパント材料を含んで構成され、前記第1ウェル(50)内の前記コンタクトウェル(58)は前記第1ウェル(50)のドーパント濃度よりも高いドーパント濃度を有する。
Description
本発明は、上述の問題点のすべてまたは少なくともいくつかを解決し、または少なくとも改善するデバイスまたは様々な方法を対象とする。
本発明は様々な変形および代替の形態をとりうるが、その特定の実施形態を例示のために図面に示し、本明細書において詳細に説明する。しかしながら、特定の実施形態についての本明細書中の説明は、開示された特定の形態に本発明を限定しようとするものではなく、むしろ反対に、添付の特許請求の範囲に規定される本発明の精神および範囲の範疇に入る、すべての変形物、均等物および代替物を含むことを意図している、ことを理解してもらいたい。
Claims (20)
- 第1型のドーパント材料でドーピングされるバルク基板(30A)と、埋め込み絶縁層(30B)と、活性層(30C)とを含んで構成されるシリコン・オン・インシュレータ基板(30)上に形成されるトランジスタ(32)と、
前記バルク基板(30A)に形成され、前記第1型のドーパント材料とは反対の型の第2型のドーパント材料でドーピングされる第1ウェル(50)と、
前記バルク基板(30A)の前記第1ウェル(50)内に形成され、前記第1型のドーパント材料と同じ型のドーパント材料でドーピングされる第2ウェル(50)と、
前記第1ウェル(50)のための電気コンタクト(60)と、
前記第2ウェル(52)のための電気コンタクト(62)とを備え、
前記トランジスタ(32)は前記第2ウェル(52)上の前記活性層(30C)に形成される、デバイス。 - 前記バルク基板(30A)の前記第1ウェル(50)内に形成されたコンタクトウェル(58)をさらに含み、前記コンタクトウェル(58)は前記第2型のドーパント材料と同じ型のドーパント材料を含んで構成され、前記第1ウェル(50)内のコンタクトウェル(58)は前記第1ウェル(50)の前記第2型のドーパント材料のドーパント濃度レベルよりも高い前記第2型のドーパント材料の濃度レベルを有する、請求項1記載のデバイス。
- 前記バルク基板(30A)の前記第2ウェル(52)内に形成されたコンタクトウェル(56)をさらに含み、前記コンタクトウェル(56)は前記第1型のドーパント材料と同じ型のドーパント材料を含んで構成され、前記第2ウェル(52)内のコンタクトウェル(56)は前記第2ウェル(52)の前記第1型のドーパント材料のドーパント濃度レベルよりも高い前記第1型のドーパント材料の濃度レベルを有する、請求項1記載のデバイス。
- 前記トランジスタは複数のソース/ドレイン領域(42)をさらに含み、前記デバイスは前記バルク基板(30A)の前記ソース/ドレイン領域(42)のそれぞれの下の前記第2ウェル(52)内に形成されたソース/ドレインウェル(54)をさらに備え、前記ソース/ドレインウェル(54)は前記第1型のドーパント材料と同じ型のドーパント材料を含んで構成され、前記第2ウェル(52)中の前記第1型のドーパント材料のドーパント濃度レベルよりも低い前記第1型のドーパント材料のドーパント濃度レベルを有する、請求項1記載のデバイス。
- 前記バルク基板(30A)はシリコンを含んで構成され、前記埋め込み絶縁層(30B)は二酸化シリコンを含んで構成され、前記活性化層(30C)はシリコンを含んで構成される、請求項1記載のデバイス。
- 前記バルクシリコン基板(30A)はおよそ1012-1016イオン/cm3の範囲のドーパント濃度レベルを有する、請求項1記載のデバイス。
- 前記第1ウェル(50)はおよそ1016-1019イオン/cm3の範囲のドーパント濃度レベルを有する、請求項1記載のデバイス。
- 前記第2ウェル(52)はおよそ1017-1020イオン/cm3の範囲のドーパント濃度レベルを有する、請求項1記載のデバイス。
- 前記第1ウェル(50)内の前記コンタクトウェル(58)はおよそ2e20イオン/cm3のドーパント濃度レベルを有する、請求項2記載のデバイス。
- 前記第2ウェル(52)内の前記コンタクトウェル(56)はおよそ2e20イオン/cm3のドーパント濃度レベルを有する、請求項2記載のデバイス。
- 前記ソース/ドレインウェル(54)はおよそ1014-1017イオン/cm3の範囲のドーパント濃度レベルを有する、請求項4記載のデバイス。
- 前記第1ウェル(50)はおよそ50-150nmの範囲の深さを持つ、請求項1記載のデバイス。
- 前記第2ウェル(52)はおよそ40-100nmの範囲の深さを持つ、請求項1記載のデバイス。
- 前記ソース/ドレインウェル(54)はおよそ10-90nmの範囲の深さを持つ、請求項4記載のデバイス。
- 第1型のドーパント材料でドーピングされるバルク基板(30A)と、埋め込み絶縁層(30B)と、活性層(30C)とを含むシリコン・オン・インシュレータ基板(30)上にトランジスタ(32)を形成する方法であって、
前記バルク基板(30A)に第1ウェル領域(50)を形成するために、前記第1型のドーパント材料とは反対の型のドーパント材料を用いて第1イオン注入処理(35)を実行するステップと、
前記バルク基板(30A)の前記第1ウェル(50)内に第2ウェル領域(52)を形成するために、前記第1型のドーパント材料と同じ型のドーパント材料を用いて第2イオン注入処理(39)を実行するステップと、
前記第1ウェル(50)のための電気コンタクト(60)を形成するステップと、
前記第2ウェル(52)のための電気コンタクト(62)を形成するステップとを含み、
前記トランジスタ(32)は前記第2ウェル(52)上の前記活性層(30C)に形成される方法。 - 前記トランジスタは複数のソース/ドレイン領域(42)をさらに含み、前記方法は、前記バルク基板(30A)の前記ソース/ドレイン領域(42)のそれぞれの下にソース/ドレインウェル(54)を形成する、前記第1型のドーパント材料とは反対の型のドーパント材料を用いた第3イオン注入処理(51)を実行するステップをさらに含み、前記ソース/ドレインウェル(54)は前記第2ウェル(52)中の前記第1型のドーパント材料のドーパント濃度レベルよりも低い前記第1型のドーパント材料のドーパント濃度レベルを有する、請求項15記載の方法。
- 前記トランジスタ(32)はゲート電極(34)をさらに含み、前記第3イオン注入処理(51)は前記ゲート電極(34)が形成された後に実行される、請求項15記載の方法。
- 前記トランジスタ(32)はゲート電極(34)およびサイドウォールスペーサ(40)をさらに含み、前記第3イオン注入処理(51)は前記サイドウォールスペーサ(40)が形成された後に実行される、請求項15記載の方法。
- 前記バルク基板(30A)の前記第1ウェル(50)内にコンタクトウェル(58)を形成するために追加のイオン注入処理(42)を実行するステップをさらに含み、前記追加のイオン注入処理(42)は前記第1型のドーパント材料とは反対の型の第2の型のドーパント材料を用いて実行され、前記コンタクトウェル(58)は前記第1ウェル(50)の前記第2型のドーパント材料のドーパント濃度レベルよりも高い前記第2型のドーパント材料のドーパント濃度レベルを有する、請求項15記載の方法。
- 前記バルク基板(30A)の前記第2ウェル(52)内にコンタクトウェル(56)を形成するために追加のイオン注入処理(47)を実行するステップをさらに含み、前記追加のイオン注入処理(47)は前記第1型のドーパント材料と同じ型のドーパント材料を用いて実行され、前記コンタクトウェル(56)は前記第2ウェル(52)の前記第1型のドーパント材料のドーパント濃度レベルよりも高い前記第1型のドーパント材料のドーパント濃度レベルを有する、請求項15記載の方法。
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US10/104,939 US6919236B2 (en) | 2002-03-21 | 2002-03-21 | Biased, triple-well fully depleted SOI structure, and various methods of making and operating same |
PCT/US2002/040398 WO2003081677A1 (en) | 2002-03-21 | 2002-12-17 | Based, triple-well fully depleted soi structure, and various methods of making and operating same |
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JP2005521264A true JP2005521264A (ja) | 2005-07-14 |
JP2005521264A5 JP2005521264A5 (ja) | 2006-08-31 |
JP4361807B2 JP4361807B2 (ja) | 2009-11-11 |
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US (2) | US6919236B2 (ja) |
EP (1) | EP1488463B1 (ja) |
JP (1) | JP4361807B2 (ja) |
KR (1) | KR100939094B1 (ja) |
CN (1) | CN100346484C (ja) |
AU (1) | AU2002361758A1 (ja) |
DE (1) | DE60224847T2 (ja) |
TW (1) | TWI270983B (ja) |
WO (1) | WO2003081677A1 (ja) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7416927B2 (en) * | 2002-03-26 | 2008-08-26 | Infineon Technologies Ag | Method for producing an SOI field effect transistor |
US7115949B2 (en) * | 2002-05-30 | 2006-10-03 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device in a semiconductor layer and structure thereof |
EP1588418A1 (de) * | 2003-01-30 | 2005-10-26 | X-FAB Semiconductor Foundries AG | Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur |
JP2005116623A (ja) * | 2003-10-03 | 2005-04-28 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4664631B2 (ja) * | 2004-08-05 | 2011-04-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
TWI240370B (en) * | 2004-08-26 | 2005-09-21 | Airoha Tech Corp | Substrate structure underlying a pad and pad structure |
CN101238580B (zh) * | 2005-08-18 | 2010-06-16 | 富士通微电子株式会社 | 半导体器件及其制造方法 |
JP2007115971A (ja) * | 2005-10-21 | 2007-05-10 | Fujitsu Ltd | 半導体装置とその製造方法 |
US7442996B2 (en) * | 2006-01-20 | 2008-10-28 | International Business Machines Corporation | Structure and method for enhanced triple well latchup robustness |
DE102007004859A1 (de) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | SOI-Bauelement mit einer Substratdiode mit Prozess toleranter Konfiguration und Verfahren zur Herstellung des SOI-Bauelements |
KR101003115B1 (ko) * | 2007-12-12 | 2010-12-21 | 주식회사 하이닉스반도체 | 플로팅 바디 캐패시터를 구비한 반도체 메모리 소자 및 그제조방법 |
US7843005B2 (en) * | 2009-02-11 | 2010-11-30 | International Business Machines Corporation | SOI radio frequency switch with reduced signal distortion |
US8421156B2 (en) * | 2010-06-25 | 2013-04-16 | International Business Machines Corporation | FET with self-aligned back gate |
FR2980640B1 (fr) * | 2011-09-26 | 2014-05-02 | Commissariat Energie Atomique | Circuit integre en technologie fdsoi avec partage de caisson et moyens de polarisation des plans de masse de dopage opposes presents dans un meme caisson |
CN103489779B (zh) | 2012-06-12 | 2016-05-11 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
US9252228B2 (en) | 2013-11-29 | 2016-02-02 | Qualcomm Incorporated | Threshold voltage adjustment in metal oxide semiconductor field effect transistor with silicon oxynitride polysilicon gate stack on fully depleted silicon-on-insulator |
US9257353B1 (en) * | 2014-10-24 | 2016-02-09 | GlobalFoundries, Inc. | Integrated circuits with test structures including bi-directional protection diodes |
FR3038775A1 (fr) | 2015-07-09 | 2017-01-13 | St Microelectronics Sa | Prise de contact substrat pour un transistor mos dans un substrat soi, en particulier fdsoi |
US9621033B2 (en) | 2015-09-09 | 2017-04-11 | Nxp Usa, Inc. | Charge pump circuit for providing multiplied voltage |
US10096708B2 (en) * | 2016-03-30 | 2018-10-09 | Stmicroelectronics Sa | Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate |
FR3053834B1 (fr) | 2016-07-05 | 2020-06-12 | Stmicroelectronics Sa | Structure de transistor |
US10109620B1 (en) * | 2017-07-26 | 2018-10-23 | Globalfoundries Inc. | Method for reducing switch on state resistance of switched-capacitor charge pump using self-generated switching back-gate bias voltage |
CN109545792B (zh) * | 2018-11-29 | 2022-01-04 | 上海华力微电子有限公司 | 一种sonos存储结构及其制造方法 |
US11444160B2 (en) | 2020-12-11 | 2022-09-13 | Globalfoundries U.S. Inc. | Integrated circuit (IC) structure with body contact to well with multiple diode junctions |
CN113594161A (zh) * | 2021-07-30 | 2021-11-02 | 广东省大湾区集成电路与系统应用研究院 | 半导体器件及其制作方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR920008834A (ko) * | 1990-10-09 | 1992-05-28 | 아이자와 스스무 | 박막 반도체 장치 |
US5359219A (en) * | 1992-12-04 | 1994-10-25 | Texas Instruments Incorporated | Silicon on insulator device comprising improved substrate doping |
JP3110262B2 (ja) * | 1993-11-15 | 2000-11-20 | 松下電器産業株式会社 | 半導体装置及び半導体装置のオペレーティング方法 |
JPH0832040A (ja) | 1994-07-14 | 1996-02-02 | Nec Corp | 半導体装置 |
JPH0887881A (ja) * | 1994-09-19 | 1996-04-02 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH08153880A (ja) | 1994-09-29 | 1996-06-11 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3462301B2 (ja) * | 1995-06-16 | 2003-11-05 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP3641511B2 (ja) * | 1995-06-16 | 2005-04-20 | 株式会社ルネサステクノロジ | 半導体装置 |
DE69733603D1 (de) * | 1997-01-23 | 2005-07-28 | St Microelectronics Srl | NMOS, negative Ladungspumpe |
US5923067A (en) * | 1997-04-04 | 1999-07-13 | International Business Machines Corporation | 3-D CMOS-on-SOI ESD structure and method |
SG67518A1 (en) * | 1997-06-30 | 1999-09-21 | Matsushita Electric Works Ltd | Solid-state relay |
JP3765163B2 (ja) * | 1997-07-14 | 2006-04-12 | ソニー株式会社 | レベルシフト回路 |
US6072217A (en) * | 1998-06-11 | 2000-06-06 | Sun Microsystems, Inc. | Tunable threshold SOI device using isolated well structure for back gate |
US6100567A (en) * | 1998-06-11 | 2000-08-08 | Sun Microsystems, Inc. | Tunable threshold SOI device using back gate and intrinsic channel region |
US6307233B1 (en) * | 1998-07-31 | 2001-10-23 | Texas Instruments Incorporated | Electrically isolated double gated transistor |
KR100302189B1 (ko) * | 1999-10-05 | 2001-11-02 | 윤종용 | 에스.오.아이(soi)구조를 갖는 반도체 소자 및 그 제조방법 |
JP3872927B2 (ja) * | 2000-03-22 | 2007-01-24 | 株式会社東芝 | 昇圧回路 |
US6406948B1 (en) * | 2000-07-13 | 2002-06-18 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate |
JP3475162B2 (ja) * | 2000-09-08 | 2003-12-08 | 三洋電機株式会社 | チャージポンプ回路 |
US6496055B2 (en) * | 2000-12-29 | 2002-12-17 | Intel Corporation | Gate enhanced tri-channel positive charge pump |
US6677805B2 (en) * | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6661042B2 (en) * | 2002-03-11 | 2003-12-09 | Monolithic System Technology, Inc. | One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region |
US7432136B2 (en) * | 2002-05-06 | 2008-10-07 | Advanced Micro Devices, Inc. | Transistors with controllable threshold voltages, and various methods of making and operating same |
-
2002
- 2002-03-21 US US10/104,939 patent/US6919236B2/en not_active Expired - Lifetime
- 2002-12-17 KR KR1020047014856A patent/KR100939094B1/ko not_active IP Right Cessation
- 2002-12-17 CN CNB028286138A patent/CN100346484C/zh not_active Expired - Fee Related
- 2002-12-17 AU AU2002361758A patent/AU2002361758A1/en not_active Abandoned
- 2002-12-17 JP JP2003579285A patent/JP4361807B2/ja not_active Expired - Fee Related
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AU2002361758A1 (en) | 2003-10-08 |
EP1488463A1 (en) | 2004-12-22 |
TW200307369A (en) | 2003-12-01 |
CN1623238A (zh) | 2005-06-01 |
US6919236B2 (en) | 2005-07-19 |
JP4361807B2 (ja) | 2009-11-11 |
TWI270983B (en) | 2007-01-11 |
DE60224847T2 (de) | 2009-02-05 |
US20050184341A1 (en) | 2005-08-25 |
EP1488463B1 (en) | 2008-01-23 |
US20030178622A1 (en) | 2003-09-25 |
DE60224847D1 (de) | 2008-03-13 |
KR100939094B1 (ko) | 2010-01-28 |
WO2003081677A1 (en) | 2003-10-02 |
KR20040108678A (ko) | 2004-12-24 |
CN100346484C (zh) | 2007-10-31 |
US7180136B2 (en) | 2007-02-20 |
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