JP2005521265A5 - - Google Patents

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Publication number
JP2005521265A5
JP2005521265A5 JP2003579286A JP2003579286A JP2005521265A5 JP 2005521265 A5 JP2005521265 A5 JP 2005521265A5 JP 2003579286 A JP2003579286 A JP 2003579286A JP 2003579286 A JP2003579286 A JP 2003579286A JP 2005521265 A5 JP2005521265 A5 JP 2005521265A5
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JP
Japan
Prior art keywords
doped region
doped
gate electrode
bulk substrate
dopant material
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Application number
JP2003579286A
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English (en)
Japanese (ja)
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JP2005521265A (ja
JP4470011B2 (ja
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Publication date
Priority claimed from US10/104,319 external-priority patent/US6780686B2/en
Application filed filed Critical
Publication of JP2005521265A publication Critical patent/JP2005521265A/ja
Publication of JP2005521265A5 publication Critical patent/JP2005521265A5/ja
Application granted granted Critical
Publication of JP4470011B2 publication Critical patent/JP4470011B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2003579286A 2002-03-21 2002-12-17 ゲート電極を備えたトランジスタを有するデバイス及びその形成方法 Expired - Lifetime JP4470011B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/104,319 US6780686B2 (en) 2002-03-21 2002-03-21 Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions
PCT/US2002/040399 WO2003081678A1 (en) 2002-03-21 2002-12-17 Doping methods for fully-depleted soi structures, and device comprising the resulting doped regions

Publications (3)

Publication Number Publication Date
JP2005521265A JP2005521265A (ja) 2005-07-14
JP2005521265A5 true JP2005521265A5 (enExample) 2006-02-09
JP4470011B2 JP4470011B2 (ja) 2010-06-02

Family

ID=28040566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003579286A Expired - Lifetime JP4470011B2 (ja) 2002-03-21 2002-12-17 ゲート電極を備えたトランジスタを有するデバイス及びその形成方法

Country Status (9)

Country Link
US (2) US6780686B2 (enExample)
JP (1) JP4470011B2 (enExample)
KR (1) KR100913830B1 (enExample)
CN (1) CN100399582C (enExample)
AU (1) AU2002361759A1 (enExample)
DE (1) DE10297679B4 (enExample)
GB (1) GB2409335B (enExample)
TW (1) TWI265559B (enExample)
WO (1) WO2003081678A1 (enExample)

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US7838875B1 (en) * 2003-01-22 2010-11-23 Tsang Dean Z Metal transistor device
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
TWI248681B (en) * 2004-03-29 2006-02-01 Imec Inter Uni Micro Electr Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel
JP4664631B2 (ja) * 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
US7230270B2 (en) * 2004-11-24 2007-06-12 Taiwan Semiconductor Manfacturing Company, Ltd. Self-aligned double gate device and method for forming same
US7605042B2 (en) * 2005-04-18 2009-10-20 Toshiba America Electronic Components, Inc. SOI bottom pre-doping merged e-SiGe for poly height reduction
US7314794B2 (en) * 2005-08-08 2008-01-01 International Business Machines Corporation Low-cost high-performance planar back-gate CMOS
US7442586B2 (en) * 2006-03-31 2008-10-28 International Business Machines Corporation SOI substrate and SOI device, and method for forming the same
US7285480B1 (en) * 2006-04-07 2007-10-23 International Business Machines Corporation Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
US7629649B2 (en) * 2006-05-09 2009-12-08 Atmel Corporation Method and materials to control doping profile in integrated circuit substrate material
JP5057804B2 (ja) 2007-03-12 2012-10-24 株式会社東芝 半導体装置
US8120110B2 (en) 2008-08-08 2012-02-21 International Business Machines Corporation Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate
US8012814B2 (en) * 2008-08-08 2011-09-06 International Business Machines Corporation Method of forming a high performance fet and a high voltage fet on a SOI substrate
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
DE102009006800B4 (de) * 2009-01-30 2013-01-31 Advanced Micro Devices, Inc. Verfahren zur Herstellung von Transistoren und entsprechendes Halbleiterbauelement
US8471340B2 (en) 2009-11-30 2013-06-25 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
US8698244B2 (en) * 2009-11-30 2014-04-15 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method
US8299545B2 (en) * 2010-01-28 2012-10-30 International Business Machines Corporation Method and structure to improve body effect and junction capacitance
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8421156B2 (en) * 2010-06-25 2013-04-16 International Business Machines Corporation FET with self-aligned back gate
US8664067B2 (en) * 2010-11-18 2014-03-04 Monolithic Power Systems, Inc. CMOS devices with reduced short channel effects
US8507989B2 (en) * 2011-05-16 2013-08-13 International Business Machine Corporation Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
JP5456090B2 (ja) * 2012-03-13 2014-03-26 株式会社東芝 半導体装置およびその製造方法
CN103779212B (zh) * 2012-10-18 2016-11-16 中国科学院微电子研究所 半导体结构及其制造方法
CN103311301B (zh) * 2013-05-09 2016-06-29 北京大学 一种抑制辐射引起背栅泄漏电流的soi器件及其制备方法
US9620617B2 (en) * 2014-09-04 2017-04-11 Newport Fab, Llc Structure and method for reducing substrate parasitics in semiconductor on insulator technology
US10062713B1 (en) 2017-09-08 2018-08-28 Nxp Usa, Inc. Devices and methods for fully depleted silicon-on-insulator back biasing
EP3742476B1 (en) * 2019-05-20 2024-11-06 Infineon Technologies AG Method of implanting an implant species into a substrate at different depths
CN112038405B (zh) * 2020-08-19 2024-06-18 深圳市紫光同创电子有限公司 场效应晶体管及其制备方法、静态随机存储器、集成电路
CN112765922B (zh) * 2020-12-31 2024-04-19 中国科学院上海微系统与信息技术研究所 采用soi衬底的射频晶体管的仿真模型
US11984479B2 (en) * 2021-02-17 2024-05-14 Analog Devices International Unlimited Company Hybrid field-effect transistor

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US5599728A (en) * 1994-04-07 1997-02-04 Regents Of The University Of California Method of fabricating a self-aligned high speed MOSFET device
US5482871A (en) * 1994-04-15 1996-01-09 Texas Instruments Incorporated Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate
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US6468852B1 (en) * 2001-08-03 2002-10-22 Micron Technology, Inc. Methods of forming field effect transistors; methods of forming DRAM circuitry

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