JP2002198529A5 - - Google Patents
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- Publication number
- JP2002198529A5 JP2002198529A5 JP2001219666A JP2001219666A JP2002198529A5 JP 2002198529 A5 JP2002198529 A5 JP 2002198529A5 JP 2001219666 A JP2001219666 A JP 2001219666A JP 2001219666 A JP2001219666 A JP 2001219666A JP 2002198529 A5 JP2002198529 A5 JP 2002198529A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- conductive type
- manufacturing
- impurity layer
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 description 52
- 239000012535 impurity Substances 0.000 description 38
- 238000000034 method Methods 0.000 description 26
- 238000004519 manufacturing process Methods 0.000 description 25
- 239000000758 substrate Substances 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001219666A JP2002198529A (ja) | 2000-10-18 | 2001-07-19 | 半導体装置およびその製造方法 |
| US09/965,479 US6524903B2 (en) | 2000-10-18 | 2001-09-28 | Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution |
| TW090124304A TW522548B (en) | 2000-10-18 | 2001-10-02 | Semiconductor device and its manufacturing method |
| KR1020010063328A KR100828790B1 (ko) | 2000-10-18 | 2001-10-15 | 반도체장치 및 그 제조방법 |
| US10/298,597 US7042051B2 (en) | 2000-10-18 | 2002-11-19 | Semiconductor device including impurity layer having a plurality of impurity peaks formed beneath the channel region |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000-317345 | 2000-10-18 | ||
| JP2000317345 | 2000-10-18 | ||
| JP2001219666A JP2002198529A (ja) | 2000-10-18 | 2001-07-19 | 半導体装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002198529A JP2002198529A (ja) | 2002-07-12 |
| JP2002198529A5 true JP2002198529A5 (enExample) | 2006-11-16 |
Family
ID=26602282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001219666A Pending JP2002198529A (ja) | 2000-10-18 | 2001-07-19 | 半導体装置およびその製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6524903B2 (enExample) |
| JP (1) | JP2002198529A (enExample) |
| KR (1) | KR100828790B1 (enExample) |
| TW (1) | TW522548B (enExample) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030064550A1 (en) * | 2001-09-28 | 2003-04-03 | Layman Paul Arthur | Method of ion implantation for achieving desired dopant concentration |
| US20030082892A1 (en) * | 2001-10-31 | 2003-05-01 | Macronix International Co., Ltd. | Method for reducing the drain coupling ratio of floating gate device |
| US6887758B2 (en) * | 2002-10-09 | 2005-05-03 | Freescale Semiconductor, Inc. | Non-volatile memory device and method for forming |
| US6815355B2 (en) * | 2002-10-09 | 2004-11-09 | Chartered Semiconductor Manufacturing Ltd. | Method of integrating L-shaped spacers in a high performance CMOS process via use of an oxide-nitride-doped oxide spacer |
| KR100496551B1 (ko) * | 2002-11-20 | 2005-06-22 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
| JP2004221246A (ja) * | 2003-01-14 | 2004-08-05 | Seiko Epson Corp | 半導体装置及びその製造方法 |
| CN100472001C (zh) * | 2003-02-25 | 2009-03-25 | 株式会社上睦可 | 硅晶片、soi衬底、硅单晶生长方法,硅晶片制造方法及soi衬底制造方法 |
| TWI235411B (en) * | 2003-07-23 | 2005-07-01 | Samsung Electronics Co Ltd | Self-aligned inner gate recess channel transistor and method of forming the same |
| US7205185B2 (en) * | 2003-09-15 | 2007-04-17 | International Busniess Machines Corporation | Self-aligned planar double-gate process by self-aligned oxidation |
| DE10345345A1 (de) * | 2003-09-19 | 2005-04-14 | Atmel Germany Gmbh | Verfahren zur Herstellung von Halbleiterbauelementen in einem Halbleitersubstrat |
| DE10345346B4 (de) * | 2003-09-19 | 2010-09-16 | Atmel Automotive Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements mit aktiven Bereichen, die durch Isolationsstrukturen voneinander getrennt sind |
| JP4469677B2 (ja) | 2004-08-04 | 2010-05-26 | パナソニック株式会社 | 半導体装置およびその製造方法 |
| US20060068556A1 (en) * | 2004-09-27 | 2006-03-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP4540438B2 (ja) * | 2004-09-27 | 2010-09-08 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| JP4854955B2 (ja) * | 2004-12-10 | 2012-01-18 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| JP5114829B2 (ja) * | 2005-05-13 | 2013-01-09 | ソニー株式会社 | 半導体装置およびその製造方法 |
| KR100764737B1 (ko) * | 2006-02-09 | 2007-10-08 | 삼성전자주식회사 | 에스램 셀 및 그 형성 방법 |
| JP2008027976A (ja) * | 2006-07-18 | 2008-02-07 | Mitsubishi Electric Corp | 薄膜トランジスタアレイ基板、その製造方法、及び表示装置 |
| JP5486781B2 (ja) * | 2007-07-19 | 2014-05-07 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| EP2042560A1 (de) * | 2007-09-19 | 2009-04-01 | Basf Se | Leichte Holzwerkstoffe mit guten mechanischen Eigenschaften und geringer Formaldehyd-Emission |
| JP2009278053A (ja) * | 2008-05-19 | 2009-11-26 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP5434158B2 (ja) * | 2009-03-11 | 2014-03-05 | セイコーエプソン株式会社 | 半導体装置の製造方法及び半導体装置 |
| US8304835B2 (en) * | 2009-03-27 | 2012-11-06 | National Semiconductor Corporation | Configuration and fabrication of semiconductor structure using empty and filled wells |
| JP5829611B2 (ja) * | 2009-09-30 | 2015-12-09 | 三重富士通セミコンダクター株式会社 | 電界効果トランジスタ及びその製造方法 |
| US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
| US8421162B2 (en) * | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
| JP2011151120A (ja) | 2010-01-20 | 2011-08-04 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
| JP2011159853A (ja) * | 2010-02-02 | 2011-08-18 | Toshiba Corp | 半導体装置およびその製造方法 |
| US8759872B2 (en) * | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
| US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
| CN111048509B (zh) * | 2014-03-28 | 2023-12-01 | 株式会社半导体能源研究所 | 半导体装置 |
| US9437500B1 (en) * | 2015-03-13 | 2016-09-06 | Freescale Semiconductor, Inc. | Method of forming supra low threshold devices |
| US9653164B2 (en) | 2015-03-13 | 2017-05-16 | Nxp Usa, Inc. | Method for integrating non-volatile memory cells with static random access memory cells and logic transistors |
| US9761525B1 (en) * | 2016-04-29 | 2017-09-12 | Globalfoundries Inc. | Multiple back gate transistor |
| CN115548126A (zh) * | 2022-12-02 | 2022-12-30 | 绍兴中芯集成电路制造股份有限公司 | Mos器件及其制造方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0734475B2 (ja) * | 1989-03-10 | 1995-04-12 | 株式会社東芝 | 半導体装置 |
| JP2668141B2 (ja) * | 1989-11-29 | 1997-10-27 | 三菱電機株式会社 | Mis型fet |
| JPH0458562A (ja) | 1990-06-28 | 1992-02-25 | Nec Corp | Mos型トランジスタ及びその製造方法 |
| JPH05259449A (ja) * | 1992-03-11 | 1993-10-08 | Toshiba Corp | Mis型電界効果トランジスタ及びその製造方法 |
| JPH09121049A (ja) * | 1995-10-25 | 1997-05-06 | Sony Corp | 半導体装置 |
| US5719081A (en) * | 1995-11-03 | 1998-02-17 | Motorola, Inc. | Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant |
| JP3543508B2 (ja) * | 1996-01-22 | 2004-07-14 | 株式会社デンソー | 半導体装置 |
| JP3575908B2 (ja) * | 1996-03-28 | 2004-10-13 | 株式会社東芝 | 半導体装置 |
| JPH10189978A (ja) * | 1996-12-20 | 1998-07-21 | Hitachi Ltd | 半導体集積回路装置 |
| US5827763A (en) * | 1997-01-30 | 1998-10-27 | Advanced Micro Devices, Inc. | Method of forming a multiple transistor channel doping using a dual resist fabrication sequence |
| US6153454A (en) * | 1997-07-09 | 2000-11-28 | Advanced Micro Devices, Inc. | Convex device with selectively doped channel |
| CN1219328C (zh) * | 1998-02-19 | 2005-09-14 | 国际商业机器公司 | 具有改善了注入剂的场效应晶体管及其制造方法 |
| KR100332107B1 (ko) * | 1999-06-29 | 2002-04-10 | 박종섭 | 반도체 소자의 트랜지스터 제조 방법 |
| US6342429B1 (en) * | 1999-12-22 | 2002-01-29 | Lsi Logic Corporation | Method of fabricating an indium field implant for punchthrough protection in semiconductor devices |
-
2001
- 2001-07-19 JP JP2001219666A patent/JP2002198529A/ja active Pending
- 2001-09-28 US US09/965,479 patent/US6524903B2/en not_active Expired - Fee Related
- 2001-10-02 TW TW090124304A patent/TW522548B/zh not_active IP Right Cessation
- 2001-10-15 KR KR1020010063328A patent/KR100828790B1/ko not_active Expired - Fee Related
-
2002
- 2002-11-19 US US10/298,597 patent/US7042051B2/en not_active Expired - Fee Related
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