US20030064550A1 - Method of ion implantation for achieving desired dopant concentration - Google Patents
Method of ion implantation for achieving desired dopant concentration Download PDFInfo
- Publication number
- US20030064550A1 US20030064550A1 US09/968,388 US96838801A US2003064550A1 US 20030064550 A1 US20030064550 A1 US 20030064550A1 US 96838801 A US96838801 A US 96838801A US 2003064550 A1 US2003064550 A1 US 2003064550A1
- Authority
- US
- United States
- Prior art keywords
- region
- material line
- doped semiconductor
- dopant concentration
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000002019 doping agent Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000005468 ion implantation Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000005540 biological transmission Effects 0.000 claims abstract description 5
- 230000001419 dependent effect Effects 0.000 claims abstract description 5
- 238000010884 ion-beam technique Methods 0.000 claims abstract 14
- 230000001154 acute effect Effects 0.000 claims abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 150000002500 ions Chemical class 0.000 claims description 18
- 230000005669 field effect Effects 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims 1
- 239000007943 implant Substances 0.000 description 30
- 108091006146 Channels Proteins 0.000 description 20
- 230000008569 process Effects 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 9
- 125000001475 halogen functional group Chemical group 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- NHWNVPNZGGXQQV-UHFFFAOYSA-J [Si+4].[O-]N=O.[O-]N=O.[O-]N=O.[O-]N=O Chemical compound [Si+4].[O-]N=O.[O-]N=O.[O-]N=O.[O-]N=O NHWNVPNZGGXQQV-UHFFFAOYSA-J 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009881 electrostatic interaction Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Definitions
- the present invention is directed to semiconductor devices incorporating junctions of varying conductivity types designed to conduct current and methods of making such devices. More specifically, the present invention is directed to metal-oxide field-effect transistors (MOSFETs) having uniquely-determinable threshold voltages and methods for fabricating integrated circuits incorporating such devices.
- MOSFETs metal-oxide field-effect transistors
- MOSFETs metal-oxide-semiconductor field effect transistors
- the substrate is doped p-type and the source and drain regions are diffused or implanted with an n+ doping.
- a thin oxide layer separates the conductive gate from the silicon surface region between the source and drain regions. No current flows from the drain to the source region unless a conducting n-type channel is formed between the two n-type regions.
- the effect of the gate voltage is to vary the conductance of the induced channel. Lowering the conductance lowers the barrier for the electrons to surmount between the source, channel and the drain. If the barrier is sufficiently reduced, by the application of a gate voltage in excess of a threshold voltage (V T ) then there is a significant electron flow from the source to the drain.
- V T a threshold voltage
- the threshold voltage is the minimum gate voltage required to induce the channel, i.e., form the inverted region to drive the MOSFET into a conducting state. For an n-channel device, the positive gate voltage must be larger than a positive threshold voltage before a conducting channel is induced.
- a p-type channel device (which is made on an n-type substrate with a p-type source and drain implants or diffusions) requires a gate voltage more negative than some threshold value to induce the required positive charge (comprising mobile holes) in the channel.
- the threshold voltage is a function of several MOSFET physical and electrical parameters, including the oxide capacitance, the oxide thickness, the difference in work functions between the gate material (typically metal or polysilicon) and the silicon substrate, the channel doping and the impurity ion charge storage within the gate oxide.
- the substrate doping concentration is varied to form MOSFETs with differing threshold voltages on a single integrated circuit.
- a substrate 9 comprises a p+ region 50 and a p-layer 52 , the latter typically grown by an epitaxial technique from the p+ region.
- MOSFETs 2 , 4 and 6 are fabricated in the substrate 9 .
- the MOSFET 2 is separated from the MOSFET 4 by a LOCOS (local oxidation on silicon substrate) region 10 .
- the MOSFET 6 is separated from the MOSFET 4 by a LOCOS region 12 .
- the MOSFETS 2 , 4 and 6 may be electrically isolated by shallow trench isolation (STI) techniques, wherein an anisotropic etch forms a trench in the region between two active devices. The is filled with an insulative material.
- STI shallow trench isolation
- the MOSFET 2 comprises a gate 14 , a source region 16 and a drain region 18 diffused in an n-type well 20 .
- the MOSFET 4 comprises a gate 28 , a source region 30 and a drain region 32 diffused in a p-type well 34 .
- the MOSFET 6 comprises a gate 38 , a source region 40 and a drain region 42 diffused in an n-type well 44 .
- the gates 14 , 28 and 38 are separated from the substrate 9 by a silicon dioxide layer 46 , also referred to as a gate oxide layer.
- FIG. 1 is intended to be a simplified representation of a portion of an integrated circuit, the various contacts, interconnects, vias and metal layers are not shown and the features are not drawn to scale. It is particularly advantageous, especially in digital applications, to fabricate a combination of n-channel and a p-channel MOSFETs on adjacent regions of a chip.
- CMOS complementary MOSFET
- This complementary MOSFET (CMOS) configuration is illustrated in the form of a basic inverter circuit in FIG. 2, comprising a PMOSFET 60 and an NMOSFET 62 .
- the drains of the MOSFETs 60 and 62 are connected together to form the output terminal (V out ).
- the input terminal (V in ) is formed by the common connection of the MOSFET gates.
- the operating voltage is designated by V D .
- the PMOSFET 60 can be implemented by the structure of the MOSFET 2 in FIG. 1.
- the NMOSFET 62 can be implemented by the structure of the MOSFET 4 of FIG. 1.
- each of the MOSFETs 2 , 4 and 6 of FIG. 1 may be designed to operate at a different operating voltage, i.e., V D /V S and/or at a different threshold voltage, V T .
- V D /V S a different operating voltage
- V T a different threshold voltage
- FIGS. 3 through 6 The prior art process of forming a plurality of MOSFETs with different threshold voltages is illustrated in FIGS. 3 through 6.
- each tub or well has a different doping density and therefore the MOSFET formed in each tub has a different threshold voltage.
- a p+ substrate 100 carries an epitaxially grown p-layer 102 in which a plurality (three in this example) of n-type tubs are formed.
- p-type tubs or wells in a p or n-type substrate.
- the tubs certain regions of the epitaxial layer 102 are masked by masks 104 , 106 , 108 and 110 , with the space between these masks defining the tub regions.
- the arrows indicate the implantation of phosphorous or arsenic to create the n-type wells.
- the implant energy is 10 to 100 keV with a dose of 1E12 to 5E14 per cm 2 .
- this implantation step forms three n-type wells, 120 , 122 and 124 , each having the same doping density. If all other physical and electrical parameters for the three wells are equivalent, then the threshold voltages at this point in the process are also equivalent.
- FIG. 4 further illustrates the application of a second implantation to the well 120 , while the wells 122 and 124 (and other areas of the substrate 100 ) are masked by masks 126 and 128 . Thus the final doping density and the threshold voltage for the MOSFET formed in the well 120 are determined by the parameters of the FIG. 4 implant into the well 120 .
- the wells 120 and 124 are masked by masks 130 and 132 , respectively.
- An additional implant step is executed for the well 122 to establish the final doping density and threshold voltage for the MOSFET formed therein.
- the wells 120 and 122 are masked with a mask 134 and the remainder of the substrate 100 is masked, as necessary, by a mask 136 .
- an additional implant is made in the well 124 for establishing its doping density and thus the threshold voltage for the MOSFET formed therein.
- MOSFETs As is well known to those skilled in the art, at this point fabrication of the MOSFETs proceeds conventionally. For each MOSFET, a gate oxide is grown or deposited followed by formation of the gate. The gate serves as a mask for a first low-dose implant to form the lightly doped drain and source regions. A relatively thick layer of silicon dioxide is then deposited, for instance, by chemical vapor deposition and certain portions thereof are anisotropically etched, leaving only two sidewall spacers adjacent the gate. The spacers serve as a mask for a high-dose dopant implant to form the source and drain regions. After a drive-in diffusion step, the source and drain regions and the adjacent lightly-doped regions are formed.
- an integrated circuit semiconductor device includes a plurality of doped tubs or wells in which the source, drain and channel regions are later formed.
- the dopant density in each well is established to produce the required threshold voltage for the MOSFET device formed in that well.
- a tilted implant is performed through patterned lines of photoresist, polysilicon, silicon dioxide, silicon nitride, or any material that blocks or impedes the transmission of implanting ions therethrough.
- Each line in the patterned layer has a different width for controlling the number of implanting ions that penetrate the patterned layer and enter the substrate in the region adjacent the line.
- ion implantation energy typically measured in keV
- more ions will penetrate a thinner line in the layer than a thicker line.
- a tub formed by implantation through an adjacent thinner pattern line has a higher doping density and the MOSFET formed therein has a higher threshold voltage.
- the method according to the present invention reduces the cost and complexity of forming MOSFETs with different threshold voltages.
- a plurality of MOSFETs with a range of threshold voltage values can be formed simultaneously with no additional masking steps.
- FIG. 1 is a cross-sectional view of a prior art MOSFET devices
- FIG. 2 is a partial schematic of a prior art CMOS integrated circuit
- FIGS. 3 through 6 illustrate, in cross-section, a prior art process for forming MOSFETs with different threshold voltages during sequential process steps
- FIGS. 7 and 8 illustrate prior art integrated circuits in schematic form
- FIGS. 9 through 17 illustrate, in cross-section, a process for forming MOSFETs with different threshold voltages according to the teachings of the present invention.
- FIG. 7 is a partial schematic of a prior art CMOS integrated circuit 168 illustrating two pairs of CMOS devices.
- PMOSFET 170 and NMOSFET 172 form a first CMOS pair;
- PMOSFET 174 and NMOSFET 176 form a second CMOS pair.
- V in 1 is the gate driving signal for the PMOSFET 170 and the NMOSFET 172 , which creates an output signal (V out 1 ) at the common drain connection.
- V in 2 is the gate signal for the CMOS pair PMOSFET 174 and NMOSFET 176 , which produces an output signal V out 2 .
- PMOSFET 170 is responsive to a drain voltage V dd.
- V dd2 is responsive to a drain voltage V dd2 .
- the drain voltages V dd1 and V dd2 may be produced off-chip or on-chip, although they are illustrated in FIG. 7 as originating from an off-chip voltage source. Because in one embodiment V dd1 and V dd2 are not equal, V out 1 is not equal to V out 2 . In a typical circuit configuration, both output signals V out 1 and V out 2 drive the next active element in a cascaded circuit chain. For instance, V out 1 can serve as the input signal V in 2 , and V out 2 can be supplied to another element in the integrated circuit 168 or sent off-chip.
- V in 1 may be produced by another circuit within the integrated circuit 168 or originate from an off-chip source.
- V dd1 and V dd2 operating voltages
- V in 1 , V in2 , V out 1 and V out 2 input/output voltages
- the CMOS pair comprising PMOSFET 170 and NMOSFET 172 may be fabricated with a first threshold voltage
- the CMOS pair PMOSFET 174 and NMOSFET 176 may be fabricated with a second threshold voltage.
- FIG. 8 illustrates another exemplary integrated circuit 178 comprising an NMOSFET device 182 and an NMOSFET device 184 .
- the input signals V g 1 and V g 2 may not be in the same voltage range and thus the NMOSFET devices 182 and 184 must each be fabricated to accommodate a different threshold voltage input signal.
- the drain terminals of both NMOSFET 182 and NMOSFET 184 are connected to a single supply voltage, V dd1 .
- V dd1 the drain terminals of both NMOSFET 182 and NMOSFET 184 are connected to a single supply voltage, V dd1 .
- the fact that each transistor is operated from the same supply voltage is not necessarily determinative of the threshold voltage required to accommodate the gate input signals. Because the MOSFET threshold voltages are chosen based on a number of design and operating characteristics of the integrated circuit, it is possible that several different threshold voltage MOSFETs will be required on a state-of-the-art integrated circuit.
- the PMOSFET 170 and NMOSFET 172 can be fabricated with a first threshold voltage, while the PMOSFET 174 and the NMOSFET 176 can be fabricated with a second threshold voltage.
- the relevance of the present invention is not limited to CMOS applications, but can instead be applied to individual MOSFETs, whether such MOSFETs are interconnected to form logic circuits, signal processing circuits, basic CMOS building block circuits or memory devices.
- the first step in forming a plurality of MOSFETs and independently determining the threshold voltage for each begins by implanting the wells or tubs.
- a substrate 200 doped p+
- a substrate 200 underlies an epitaxially grown p-layer 202 .
- Mask elements 204 , 206 , 208 and 210 are placed over the epitaxial layer 202 and phosphorous or arsenic dopant ions are implanted into the epitaxial layer 202 in the open spaces between the mask elements 204 , 206 , 208 and 210 .
- FIG. 10 showing three n-type wells 220 , 222 and 224 .
- each well 220 , 222 and 224 is isolated from the adjacent well by a local oxidation of silicon (LOCOS) region 225 and 226 .
- LOC local oxidation of silicon
- shallow trench isolation can be utilized.
- a layer of photoresist, silicon nitride, silicon dioxide or other material that is partially transmissive to the ions to be implanted through the mask element is formed over the epitaxial layer 202 .
- a mask element having a plurality of different-width lines is created, and the mask is used to pattern the layer such that a line is located proximate each of the n-type wells that are to be implanted, for example, the n-type wells 220 , 222 and 224 .
- three such patterned lines 230 , 232 and 234 are shown.
- the lines are of a different width, which in turn controls the doping density in the adjacent well due to the use of a tilted ion implant through the lines. Tilt angles of between about 7° and 60° are typical, although tilt angles between 1° and 89° are possible.
- the arrowheads 236 , 238 and 240 represent the tilted implantation of dopant ions in the wells 220 , 222 and 224 respectively.
- Some of the ions are absorbed by the lines 230 , 232 and 234 , where the absorption rate is a function of the individual line width and the line material (each candidate material has a unique transmission coefficient for a specific ion).
- the well 222 receives a lower implant doping than the well 224 , because the line 232 is wider than the line 234 .
- the threshold voltage for the MOSFET to be formed in the well 222 is lower than the threshold voltage of the MOSFET to be formed in the well 224 .
- the line widths and material are selected to achieve the required MOSFET threshold voltage by controlling the implanted dopant density. Since the MOSFET channel region is formed in the well, MOSFETs with different threshold voltages can be fabricated throughout the integrated circuit using a single mask to form lines of varying width.
- the region of the well nearest the line may receive a higher implant dose than a region farther from the line as the implanting ions travel a greater distance in the masking layer in the latter case.
- FIG. 12A illustrating a mask line 260 positioned above a semiconductor substrate 262 , and a plurality of implanting rays 264 .
- the mask line is sufficiently high to permit all the implanting rays 264 to pass therethrough.
- FIG. 12B illustrates the doping profiles in the semiconductor substrate 262 ; the implant profile is represented by a solid line and the post-diffusion profile as a dashed line. To the extent this creates a lateral variation in the doping profile, the device threshold voltage is determined by the composite or average doping density in the semiconductor substrate 262 .
- a mask line 270 is positioned above a semiconductor substrate 272 , but in this case the mask line 270 is not high enough for all the implant rays 274 to pass therethrough. Thus a number of the implant rays 274 pass through the mask line 270 and others pass above the mask 270 .
- the resulting dopant profiles are illustrated in FIG. 13B, where the implanted profile is represented by a solid line and the post-diffusion profile by a dashed line.
- the device threshold voltage is determined by the average or composite doping density in the semiconductor substrate 272 .
- a second implant is performed to create a relatively uniform dopant distribution across the well.
- a mirror image of the FIG. 11 line pattern, comprising lines 290 , 292 and 294 is formed on the opposite side of each well 220 , 222 and 224 , and a second tilted implant is performed from the opposite side as shown. Having been implanted from both sides of the well, the dopant density across the well is relatively uniform.
- the process according to the present invention is considerably less expensive than the prior art process, which requires multiple masks to form MOSFETs with different threshold voltages.
- the lines 230 , 232 , and 234 are formed of photoresist material.
- the lines are formed from polysilicon, silicon nitrite or silicon dioxide, all of which are common expedients used in conventional integrated circuit fabrication. To determine the width of each line, consideration must be given to the line material employed, as each material has a different transmission characteristic for the ions to be implanted.
- the fabrication process proceeds according to conventional MOSFET fabrication steps.
- a gate oxide is grown or deposited and the gate is then formed.
- the gate serves as a mask for a first low-dose implant to form the lightly doped drain and source regions, also referred to as drain and source extensions.
- a relatively thick layer of silicon dioxide is then deposited, for instance, by chemical vapor deposition, and anisotropically etched, leaving only two sidewall spacers adjacent the gate.
- the spacers serve as a mask for a high-dose dopant implant to form the source and drain regions. After drive-in diffusion, the source and drain regions and the adjacent lightly-doped regions are formed.
- drain induced barrier lowering This phenomena, which occurs when there is unintended electrostatic interaction between the source and drain regions, is typically caused by improperly scaling of the device regions, i.e., the source and drain regions are too thick or the channel doping is too low.
- the result of drain induced barrier loading is punchthrough leakage or breakdown between the source and the drain, and the loss of gate control over the channel current.
- the source and drain junctions must be made sufficiently shallow as the channel lengths are reduced.
- the channel doping must be sufficiently high to prevent the drain from exercising control over the source junction, but increasing the doping concentration throughout the channel region may undesirably increase the threshold voltage.
- the channel doping is increased by performing localized dopant implants in the channel near the source and drain regions.
- the localized implants are known as halo or pocket implants.
- the higher doping near the source and drain regions reduces the source and drain depletion width and prevents interaction between these two regions.
- the halo process uses a tilted implant geometry and is typically performed after gate formation. The implant results in a non-uniform lateral profile under the gate, while the lateral profile in the source and drain regions remains relatively uniform.
- FIG. 15 illustrates such a halo implant in a semiconductor substrate 300 .
- Implanting adjacent a gate mask 302 (i.e., the gate serves as the mask) over a region 304 of the semiconductor substrate 300 limits the doping concentration within the region 304 .
- a line 310 in FIG. 15B represents an exemplary dopant concentration profile within the semiconductor substrate 300 .
- the dopant concentration is illustrated by a line 310 .
- the doping profile outside the region 304 is relatively uniform, then becomes non-uniform under the gate mask 302 .
- the region 304 represents the channel and the region of uniform doping concentration represents either the source or drain regions.
- FIG. 16A The teachings of the present invention can be used in conjunction with the halo implant as follows.
- two mask lines 350 and 352 overlie a substrate 354 , including a tub or well region 355 of a MOSFET. Dashed lines illustrate the approximate location of the source/drain regions 356 and 358 , which will be formed at a later stage in the process in the tub region 355 .
- Ion implant rays 360 and 362 pass through the masked lines 350 and 352 , respectively, to dope the tub 355 creating the doping profile illustrated in FIG. 16B, representing the doping profile along a horizontal plane through the source/drain regions 356 and 358 .
- a halo implant is performed using a gate mask 370 and implanting ion rays 372 and 374 as illustrated in FIG. 17A.
- the initial doping concentration is illustrated by a line 376 resulting from the process illustrated in FIG. 16A.
- the halo concentration is illustrated by a line 378 and the total concentration by a line 380 .
- the net dopant concentration in the source/drain regions 356 and 358 is about two orders of magnitude greater than the concentration in the tub regions 355 below the source/drain regions 356 / 358 .
- the latter concentration is illustrated in FIG. 17C. Note that it has the same shape as the concentration illustrated in FIG. 17B by the line 374 .
- the dopant profiles in FIG. 17B also represent the z-direction (i.e., into the plane of the page) dopant concentrations.
- the dopant profile of FIG. 17B is advantageous to reduce narrow width effects in MOSFETs having a gate width of less than about lm. Specifically, one negative narrow width effect is an increase in the threshold voltage as the channel width decreases.
- a process has been described as useful for forming MOSFET tubs wherein the tubs comprise the channel region and have a controlled dopant density. While specific applications of the invention have been illustrated, the principals disclosed herein provide a basis for practicing the invention in a variety of ways and in a variety circuit structures, including structures formed with Group III-V compounds and other semiconductor materials. Although the exemplary embodiments pertain to tub-based MOSFETs, the teachings of the present invention can be applied to any devices or device region where the device characteristics are dependent on the doping concentration. For example, the dopant concentrations of silicon-on-insulator and bipolar junction transistors regions can be controlled by the tilted implant through a material layer as discussed above. For example, bipolar junction transistors with different gain values can be formed in an integrated circuit by controlling the base doping concentration using the techniques of the present invention. Also. numerous variations are possible within the scope of the invention, which is limited only by the claims that follow.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- The present invention is directed to semiconductor devices incorporating junctions of varying conductivity types designed to conduct current and methods of making such devices. More specifically, the present invention is directed to metal-oxide field-effect transistors (MOSFETs) having uniquely-determinable threshold voltages and methods for fabricating integrated circuits incorporating such devices.
- As is known to those skilled in the art, most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral orientation, with the current flowing parallel to the plane of the substrate or body surface in a channel between a source region and a drain region.
- For an enhancement-mode n-channel MOSFET, the substrate is doped p-type and the source and drain regions are diffused or implanted with an n+ doping. A thin oxide layer separates the conductive gate from the silicon surface region between the source and drain regions. No current flows from the drain to the source region unless a conducting n-type channel is formed between the two n-type regions. When a positive voltage is applied to the gate relative to the substrate which is typically connected to the source, positive charges are in effect deposited on the gate metal and in response, negative charges are induced in the underlying silicon. These negative charges, that is mobile electrons, are formed within a thin inverted surface region of the silicon surface. These induced mobile electrons form the channel of the MOSFET and allow current to flow from the drain to the source. The effect of the gate voltage is to vary the conductance of the induced channel. Lowering the conductance lowers the barrier for the electrons to surmount between the source, channel and the drain. If the barrier is sufficiently reduced, by the application of a gate voltage in excess of a threshold voltage (VT) then there is a significant electron flow from the source to the drain. The threshold voltage is the minimum gate voltage required to induce the channel, i.e., form the inverted region to drive the MOSFET into a conducting state. For an n-channel device, the positive gate voltage must be larger than a positive threshold voltage before a conducting channel is induced. Similarly, in a p-type channel device (which is made on an n-type substrate with a p-type source and drain implants or diffusions) requires a gate voltage more negative than some threshold value to induce the required positive charge (comprising mobile holes) in the channel.
- The threshold voltage is a function of several MOSFET physical and electrical parameters, including the oxide capacitance, the oxide thickness, the difference in work functions between the gate material (typically metal or polysilicon) and the silicon substrate, the channel doping and the impurity ion charge storage within the gate oxide. As will be discussed below, and according to the prior art, typically the substrate doping concentration is varied to form MOSFETs with differing threshold voltages on a single integrated circuit.
- A plurality of planar n-channel MOSFET active devices fabricated on an integrated circuit chip are shown in the FIG. 1 cross-sectional view. A
substrate 9 comprises ap+ region 50 and a p-layer 52, the latter typically grown by an epitaxial technique from the p+ region.MOSFETs substrate 9. TheMOSFET 2 is separated from the MOSFET 4 by a LOCOS (local oxidation on silicon substrate) region 10. Similarly, theMOSFET 6 is separated from the MOSFET 4 by a LOCOS region 12. Alternatively, theMOSFETS - The
MOSFET 2 comprises agate 14, asource region 16 and a drain region 18 diffused in an n-type well 20. The MOSFET 4 comprises agate 28, asource region 30 and adrain region 32 diffused in a p-type well 34. Finally, theMOSFET 6 comprises agate 38, asource region 40 and a drain region 42 diffused in an n-type well 44. Thegates substrate 9 by a silicon dioxide layer 46, also referred to as a gate oxide layer. - As FIG. 1 is intended to be a simplified representation of a portion of an integrated circuit, the various contacts, interconnects, vias and metal layers are not shown and the features are not drawn to scale. It is particularly advantageous, especially in digital applications, to fabricate a combination of n-channel and a p-channel MOSFETs on adjacent regions of a chip. This complementary MOSFET (CMOS) configuration is illustrated in the form of a basic inverter circuit in FIG. 2, comprising a PMOSFET60 and an NMOSFET 62. The drains of the
MOSFETs MOSFET 2 in FIG. 1. The NMOSFET 62 can be implemented by the structure of the MOSFET 4 of FIG. 1. - State-of-the-art integrated circuit fabrication combines many different functions and subsystems onto a single chip, for example, combining different types of logic circuits, logic families and memory elements. For optimal performance and minimal power consumption individual devices on the integrated circuit may be operated at different operating voltages, i.e., the VD and VS values. Thus, the active devices must be fabricated with the necessary physical characteristics to accommodate the selected operating voltage. But in creating physical devices with these characteristics, it is also desirable to minimize and simplify the number of fabrication process steps.
- For example, each of the
MOSFETs - Given that there may be multiple operating voltages on a chip, there may also be multiple output voltages produced by the active elements and circuits of the chip. Thus the input circuit or device responsive to the preceding output voltage must be able to accommodate that output voltage and the active device must be designed to turn-on at the appropriate input voltage. For MOSFET and junction field-effect devices (JFETs) this turn-on voltage is the threshold voltage, the value of which is established by certain physical parameters of the device, as discussed above.
- The prior art process of forming a plurality of MOSFETs with different threshold voltages is illustrated in FIGS. 3 through 6. At the conclusion of this process, each tub or well has a different doping density and therefore the MOSFET formed in each tub has a different threshold voltage. As shown in FIG. 3, a
p+ substrate 100 carries an epitaxially grown p-layer 102 in which a plurality (three in this example) of n-type tubs are formed. Those skilled in the art recognize that the concepts presented are also applicable to the formation of p-type tubs or wells in a p or n-type substrate. To form the tubs, certain regions of theepitaxial layer 102 are masked bymasks 104, 106, 108 and 110, with the space between these masks defining the tub regions. The arrows indicate the implantation of phosphorous or arsenic to create the n-type wells. Typically, the implant energy is 10 to 100 keV with a dose of 1E12 to 5E14 per cm2. - As shown in FIG. 4, this implantation step forms three n-type wells,120, 122 and 124, each having the same doping density. If all other physical and electrical parameters for the three wells are equivalent, then the threshold voltages at this point in the process are also equivalent. FIG. 4 further illustrates the application of a second implantation to the
well 120, while thewells 122 and 124 (and other areas of the substrate 100) are masked bymasks well 120 are determined by the parameters of the FIG. 4 implant into thewell 120. - Continuing with FIG. 5, the
wells masks 130 and 132, respectively. An additional implant step is executed for thewell 122 to establish the final doping density and threshold voltage for the MOSFET formed therein. Finally, as shown in FIG. 6, thewells mask 134 and the remainder of thesubstrate 100 is masked, as necessary, by amask 136. Now an additional implant is made in thewell 124 for establishing its doping density and thus the threshold voltage for the MOSFET formed therein. Although this process is readily extendable to any number of MOSFETs on an integrated circuit, note that it requires a number of unique masks and masking steps based on the number of threshold voltages required on the integrated circuit. It is always desirable in the fabrication of integrated circuits to reduce the number of masks, as they are expensive to design and manufacture, and the number of fabrication process steps. - As is well known to those skilled in the art, at this point fabrication of the MOSFETs proceeds conventionally. For each MOSFET, a gate oxide is grown or deposited followed by formation of the gate. The gate serves as a mask for a first low-dose implant to form the lightly doped drain and source regions. A relatively thick layer of silicon dioxide is then deposited, for instance, by chemical vapor deposition and certain portions thereof are anisotropically etched, leaving only two sidewall spacers adjacent the gate. The spacers serve as a mask for a high-dose dopant implant to form the source and drain regions. After a drive-in diffusion step, the source and drain regions and the adjacent lightly-doped regions are formed.
- To provide further advances in the formation of multiple threshold voltages for semiconductor devices, a method is provided for forming MOSFET devices having different threshold voltage values.
- According to one embodiment of the invention, an integrated circuit semiconductor device includes a plurality of doped tubs or wells in which the source, drain and channel regions are later formed. The dopant density in each well is established to produce the required threshold voltage for the MOSFET device formed in that well. To create different doping levels in the tubs, a tilted implant is performed through patterned lines of photoresist, polysilicon, silicon dioxide, silicon nitride, or any material that blocks or impedes the transmission of implanting ions therethrough. Each line in the patterned layer has a different width for controlling the number of implanting ions that penetrate the patterned layer and enter the substrate in the region adjacent the line. For the same ion implantation energy (typically measured in keV) more ions will penetrate a thinner line in the layer than a thicker line. Thus a tub formed by implantation through an adjacent thinner pattern line has a higher doping density and the MOSFET formed therein has a higher threshold voltage.
- The method according to the present invention reduces the cost and complexity of forming MOSFETs with different threshold voltages. A plurality of MOSFETs with a range of threshold voltage values can be formed simultaneously with no additional masking steps.
- The present invention can be more easily understood and the further advantages and uses thereof more readily apparent, when considered in view of the description of the preferred embodiments and the following figures in which:
- FIG. 1 is a cross-sectional view of a prior art MOSFET devices;
- FIG. 2 is a partial schematic of a prior art CMOS integrated circuit;
- FIGS. 3 through 6 illustrate, in cross-section, a prior art process for forming MOSFETs with different threshold voltages during sequential process steps;
- FIGS. 7 and 8 illustrate prior art integrated circuits in schematic form;
- FIGS. 9 through 17 illustrate, in cross-section, a process for forming MOSFETs with different threshold voltages according to the teachings of the present invention.
- In accordance with common practice, the various described features are not drawn to scale, but are drawn to emphasize specific features relevant to the invention. Reference characters denote like elements throughout the figures and text.
- FIG. 7 is a partial schematic of a prior art CMOS integrated
circuit 168 illustrating two pairs of CMOS devices. PMOSFET 170 and NMOSFET 172 form a first CMOS pair; PMOSFET 174 andNMOSFET 176 form a second CMOS pair. Vin1 is the gate driving signal for the PMOSFET 170 and the NMOSFET 172, which creates an output signal (Vout1 ) at the common drain connection. Vin2 is the gate signal for the CMOS pair PMOSFET 174 andNMOSFET 176, which produces an output signal Vout2 . Note further that PMOSFET 170 is responsive to a drain voltage Vdd., and PMOSFET 174 is responsive to a drain voltage Vdd2. The drain voltages Vdd1 and Vdd2 may be produced off-chip or on-chip, although they are illustrated in FIG. 7 as originating from an off-chip voltage source. Because in one embodiment Vdd1 and Vdd2 are not equal, Vout1 is not equal to Vout2 . In a typical circuit configuration, both output signals Vout1 and Vout2 drive the next active element in a cascaded circuit chain. For instance, Vout1 can serve as the input signal Vin2 , and Vout2 can be supplied to another element in theintegrated circuit 168 or sent off-chip. Vin1 may be produced by another circuit within theintegrated circuit 168 or originate from an off-chip source. In any case, it is clear that the use of different operating voltages (Vdd1 and Vdd2) and input/output voltages (Vin1 , Vin2, Vout1 and Vout2 ) may require the formation of MOSFETs with different threshold voltages. As a result, for example, the CMOS pair comprising PMOSFET 170 and NMOSFET 172 may be fabricated with a first threshold voltage and the CMOS pair PMOSFET 174 andNMOSFET 176 may be fabricated with a second threshold voltage. - FIG. 8 illustrates another exemplary
integrated circuit 178 comprising anNMOSFET device 182 and anNMOSFET device 184. As in FIG. 7, the input signals Vg1 and Vg2 may not be in the same voltage range and thus theNMOSFET devices NMOSFET 182 andNMOSFET 184 are connected to a single supply voltage, Vdd1. The fact that each transistor is operated from the same supply voltage is not necessarily determinative of the threshold voltage required to accommodate the gate input signals. Because the MOSFET threshold voltages are chosen based on a number of design and operating characteristics of the integrated circuit, it is possible that several different threshold voltage MOSFETs will be required on a state-of-the-art integrated circuit. - With reference to FIG. 7, it can be seen that the PMOSFET170 and NMOSFET 172 can be fabricated with a first threshold voltage, while the PMOSFET 174 and the
NMOSFET 176 can be fabricated with a second threshold voltage. As will be appreciated by application of the invention to the circuit of FIG. 8, the relevance of the present invention is not limited to CMOS applications, but can instead be applied to individual MOSFETs, whether such MOSFETs are interconnected to form logic circuits, signal processing circuits, basic CMOS building block circuits or memory devices. - As shown in FIG. 9, the first step in forming a plurality of MOSFETs and independently determining the threshold voltage for each, begins by implanting the wells or tubs. In FIG. 9, a substrate200 (doped p+) underlies an epitaxially grown p-
layer 202.Mask elements epitaxial layer 202 and phosphorous or arsenic dopant ions are implanted into theepitaxial layer 202 in the open spaces between themask elements type wells region - A layer of photoresist, silicon nitride, silicon dioxide or other material that is partially transmissive to the ions to be implanted through the mask element is formed over the
epitaxial layer 202. A mask element having a plurality of different-width lines is created, and the mask is used to pattern the layer such that a line is located proximate each of the n-type wells that are to be implanted, for example, the n-type wells patterned lines - The
arrowheads wells lines line 232 is wider than theline 234. As a result, the threshold voltage for the MOSFET to be formed in the well 222 is lower than the threshold voltage of the MOSFET to be formed in thewell 224. The line widths and material are selected to achieve the required MOSFET threshold voltage by controlling the implanted dopant density. Since the MOSFET channel region is formed in the well, MOSFETs with different threshold voltages can be fabricated throughout the integrated circuit using a single mask to form lines of varying width. - It is noted that the region of the well nearest the line may receive a higher implant dose than a region farther from the line as the implanting ions travel a greater distance in the masking layer in the latter case. See the example of FIG. 12A, illustrating a
mask line 260 positioned above asemiconductor substrate 262, and a plurality of implantingrays 264. Note that the mask line is sufficiently high to permit all the implantingrays 264 to pass therethrough. FIG. 12B illustrates the doping profiles in thesemiconductor substrate 262; the implant profile is represented by a solid line and the post-diffusion profile as a dashed line. To the extent this creates a lateral variation in the doping profile, the device threshold voltage is determined by the composite or average doping density in thesemiconductor substrate 262. - In the embodiment of FIG. 13A, a mask line270 is positioned above a
semiconductor substrate 272, but in this case the mask line 270 is not high enough for all the implant rays 274 to pass therethrough. Thus a number of the implant rays 274 pass through the mask line 270 and others pass above the mask 270. The resulting dopant profiles are illustrated in FIG. 13B, where the implanted profile is represented by a solid line and the post-diffusion profile by a dashed line. In this embodiment, the device threshold voltage is determined by the average or composite doping density in thesemiconductor substrate 272. - In another embodiment of the present invention, a second implant is performed to create a relatively uniform dopant distribution across the well. As shown in FIG. 14, a mirror image of the FIG. 11 line pattern, comprising
lines 290, 292 and 294 is formed on the opposite side of each well 220, 222 and 224, and a second tilted implant is performed from the opposite side as shown. Having been implanted from both sides of the well, the dopant density across the well is relatively uniform. - Because a single mask is typically used to pattern the line width throughout the integrated circuit (or two masks if a more uniform dopant density is desired), the process according to the present invention is considerably less expensive than the prior art process, which requires multiple masks to form MOSFETs with different threshold voltages. In one embodiment of the present invention, the
lines - From this point, the fabrication process proceeds according to conventional MOSFET fabrication steps. For each MOSFET, a gate oxide is grown or deposited and the gate is then formed. The gate serves as a mask for a first low-dose implant to form the lightly doped drain and source regions, also referred to as drain and source extensions. A relatively thick layer of silicon dioxide is then deposited, for instance, by chemical vapor deposition, and anisotropically etched, leaving only two sidewall spacers adjacent the gate. The spacers serve as a mask for a high-dose dopant implant to form the source and drain regions. After drive-in diffusion, the source and drain regions and the adjacent lightly-doped regions are formed.
- As the MOSFET dimensions continue to shrink, certain disadvantageous operational characteristics develop, including drain induced barrier lowering. This phenomena, which occurs when there is unintended electrostatic interaction between the source and drain regions, is typically caused by improperly scaling of the device regions, i.e., the source and drain regions are too thick or the channel doping is too low. The result of drain induced barrier loading is punchthrough leakage or breakdown between the source and the drain, and the loss of gate control over the channel current. To avoid drain induced barrier lowering, the source and drain junctions must be made sufficiently shallow as the channel lengths are reduced. Also, the channel doping must be sufficiently high to prevent the drain from exercising control over the source junction, but increasing the doping concentration throughout the channel region may undesirably increase the threshold voltage. Thus the channel doping is increased by performing localized dopant implants in the channel near the source and drain regions. The localized implants are known as halo or pocket implants. The higher doping near the source and drain regions reduces the source and drain depletion width and prevents interaction between these two regions. The halo process uses a tilted implant geometry and is typically performed after gate formation. The implant results in a non-uniform lateral profile under the gate, while the lateral profile in the source and drain regions remains relatively uniform.
- FIG. 15 illustrates such a halo implant in a
semiconductor substrate 300. Implanting adjacent a gate mask 302 (i.e., the gate serves as the mask) over aregion 304 of thesemiconductor substrate 300 limits the doping concentration within theregion 304. Aline 310 in FIG. 15B represents an exemplary dopant concentration profile within thesemiconductor substrate 300. After the halo implant, the dopant concentration is illustrated by aline 310. As shown, the doping profile outside theregion 304 is relatively uniform, then becomes non-uniform under thegate mask 302. As applied to a MOSFET device, theregion 304 represents the channel and the region of uniform doping concentration represents either the source or drain regions. - The teachings of the present invention can be used in conjunction with the halo implant as follows. As shown in FIG. 16A, two
mask lines substrate 354, including a tub orwell region 355 of a MOSFET. Dashed lines illustrate the approximate location of the source/drain regions tub region 355. Ion implant rays 360 and 362 pass through themasked lines tub 355 creating the doping profile illustrated in FIG. 16B, representing the doping profile along a horizontal plane through the source/drain regions - Next, a halo implant is performed using a
gate mask 370 and implantingion rays line 376 resulting from the process illustrated in FIG. 16A. The halo concentration is illustrated by aline 378 and the total concentration by aline 380. The net dopant concentration in the source/drain regions tub regions 355 below the source/drain regions 356/358. The latter concentration is illustrated in FIG. 17C. Note that it has the same shape as the concentration illustrated in FIG. 17B by theline 374. The dopant profiles in FIG. 17B also represent the z-direction (i.e., into the plane of the page) dopant concentrations. - The dopant profile of FIG. 17B is advantageous to reduce narrow width effects in MOSFETs having a gate width of less than about lm. Specifically, one negative narrow width effect is an increase in the threshold voltage as the channel width decreases. The dopant profile of FIG. 17B, with the higher concentrations in the regions away from the gate, reduces this threshold voltage increase.
- Simulation results according to the present invention have shown that with a polysilicon line width of 0.65 micrometers, an implanted surface doping concentration of 1E17/cm3 is produced, and assuming certain physical characteristics for the simulated MOSFET, the resulting threshold voltage is 0.025 volts. When the line width is changed to 0.20 micrometers, the surface doping concentration is 7E17/cm3 and the simulated threshold voltage is 0.400 volts.
- A process has been described as useful for forming MOSFET tubs wherein the tubs comprise the channel region and have a controlled dopant density. While specific applications of the invention have been illustrated, the principals disclosed herein provide a basis for practicing the invention in a variety of ways and in a variety circuit structures, including structures formed with Group III-V compounds and other semiconductor materials. Although the exemplary embodiments pertain to tub-based MOSFETs, the teachings of the present invention can be applied to any devices or device region where the device characteristics are dependent on the doping concentration. For example, the dopant concentrations of silicon-on-insulator and bipolar junction transistors regions can be controlled by the tilted implant through a material layer as discussed above. For example, bipolar junction transistors with different gain values can be formed in an integrated circuit by controlling the base doping concentration using the techniques of the present invention. Also. numerous variations are possible within the scope of the invention, which is limited only by the claims that follow.
Claims (30)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/968,388 US20030064550A1 (en) | 2001-09-28 | 2001-09-28 | Method of ion implantation for achieving desired dopant concentration |
TW091119022A TW564487B (en) | 2001-09-28 | 2002-08-22 | Method of ION implantation for achieving desired dopant concentration |
GB0510245A GB2411292B (en) | 2001-09-28 | 2002-08-30 | Semiconductor devices having field effect transistors with desired dopant concentration |
GB0220202A GB2383189B (en) | 2001-09-28 | 2002-08-30 | Method of ion implantation for achieving desired dopant concentration |
JP2002280434A JP4631097B2 (en) | 2001-09-28 | 2002-09-26 | Ion implantation method to achieve desired dopant concentration |
KR1020020059060A KR100918182B1 (en) | 2001-09-28 | 2002-09-28 | Method of ion implantation for achieving desired dopant concentration |
US10/619,058 US7049199B2 (en) | 2001-09-28 | 2003-07-14 | Method of ion implantation for achieving desired dopant concentration |
JP2010038787A JP5762687B2 (en) | 2001-09-28 | 2010-02-24 | Ion implantation method to achieve desired dopant concentration |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/968,388 US20030064550A1 (en) | 2001-09-28 | 2001-09-28 | Method of ion implantation for achieving desired dopant concentration |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/619,058 Division US7049199B2 (en) | 2001-09-28 | 2003-07-14 | Method of ion implantation for achieving desired dopant concentration |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030064550A1 true US20030064550A1 (en) | 2003-04-03 |
Family
ID=25514203
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/968,388 Abandoned US20030064550A1 (en) | 2001-09-28 | 2001-09-28 | Method of ion implantation for achieving desired dopant concentration |
US10/619,058 Expired - Lifetime US7049199B2 (en) | 2001-09-28 | 2003-07-14 | Method of ion implantation for achieving desired dopant concentration |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/619,058 Expired - Lifetime US7049199B2 (en) | 2001-09-28 | 2003-07-14 | Method of ion implantation for achieving desired dopant concentration |
Country Status (5)
Country | Link |
---|---|
US (2) | US20030064550A1 (en) |
JP (2) | JP4631097B2 (en) |
KR (1) | KR100918182B1 (en) |
GB (1) | GB2383189B (en) |
TW (1) | TW564487B (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6921690B2 (en) * | 2001-12-20 | 2005-07-26 | Intersil Americas Inc. | Method of fabricating enhanced EPROM structures with accentuated hot electron generation regions |
KR100598035B1 (en) * | 2004-02-24 | 2006-07-07 | 삼성전자주식회사 | Manufacturing method of charge transfer image element |
JP4168995B2 (en) * | 2004-09-30 | 2008-10-22 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
US20060240651A1 (en) * | 2005-04-26 | 2006-10-26 | Varian Semiconductor Equipment Associates, Inc. | Methods and apparatus for adjusting ion implant parameters for improved process control |
KR100675891B1 (en) | 2005-05-04 | 2007-02-02 | 주식회사 하이닉스반도체 | Apparatus and method of implanting ions partially |
JP4959990B2 (en) * | 2006-03-01 | 2012-06-27 | 株式会社東芝 | Semiconductor device |
JP4812480B2 (en) * | 2006-03-22 | 2011-11-09 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US7824973B2 (en) * | 2008-10-02 | 2010-11-02 | Infineon Technologies Ag | Method of forming a semiconductor device and semiconductor device thereof |
JP2016051812A (en) * | 2014-08-29 | 2016-04-11 | キヤノン株式会社 | Junction field effect transistor manufacturing method, semiconductor device manufacturing method, imaging device manufacturing method, junction field effect transistor and imaging device |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4042843A (en) * | 1975-06-05 | 1977-08-16 | Electronic Arrays, Inc. | Voltage level adaption in MOSFET chips |
US4315781A (en) * | 1980-04-23 | 1982-02-16 | Hughes Aircraft Company | Method of controlling MOSFET threshold voltage with self-aligned channel stop |
JPH045861A (en) * | 1990-04-23 | 1992-01-09 | Mitsubishi Electric Corp | Semiconductor device |
US5223445A (en) * | 1990-05-30 | 1993-06-29 | Matsushita Electric Industrial Co., Ltd. | Large angle ion implantation method |
KR940004446B1 (en) * | 1990-11-05 | 1994-05-25 | 미쓰비시뎅끼 가부시끼가이샤 | Method of making semiconductor device |
JPH05183159A (en) * | 1992-01-07 | 1993-07-23 | Fujitsu Ltd | Semiconductor device and fabrication thereof |
US5372957A (en) * | 1993-07-22 | 1994-12-13 | Taiwan Semiconductor Manufacturing Company | Multiple tilted angle ion implantation MOSFET method |
US5444007A (en) * | 1994-08-03 | 1995-08-22 | Kabushiki Kaisha Toshiba | Formation of trenches having different profiles |
JPH08162424A (en) * | 1994-12-07 | 1996-06-21 | Kawasaki Steel Corp | Manufacture of semiconductor device |
US5668018A (en) * | 1995-06-07 | 1997-09-16 | International Business Machines Corporation | Method for defining a region on a wall of a semiconductor structure |
EP0789401A3 (en) * | 1995-08-25 | 1998-09-16 | Matsushita Electric Industrial Co., Ltd. | LD MOSFET or MOSFET with an integrated circuit containing thereof and manufacturing method |
JPH09246396A (en) * | 1996-03-07 | 1997-09-19 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JP3222380B2 (en) * | 1996-04-25 | 2001-10-29 | シャープ株式会社 | Field effect transistor and CMOS transistor |
US6163053A (en) * | 1996-11-06 | 2000-12-19 | Ricoh Company, Ltd. | Semiconductor device having opposite-polarity region under channel |
US6020244A (en) * | 1996-12-30 | 2000-02-01 | Intel Corporation | Channel dopant implantation with automatic compensation for variations in critical dimension |
US5827763A (en) * | 1997-01-30 | 1998-10-27 | Advanced Micro Devices, Inc. | Method of forming a multiple transistor channel doping using a dual resist fabrication sequence |
JPH10335658A (en) * | 1997-06-04 | 1998-12-18 | Nec Corp | Mosfet |
US6153454A (en) * | 1997-07-09 | 2000-11-28 | Advanced Micro Devices, Inc. | Convex device with selectively doped channel |
JPH11121394A (en) * | 1997-10-16 | 1999-04-30 | Toshiba Corp | Method of manufacturing semiconductor device |
US6187619B1 (en) * | 1998-02-17 | 2001-02-13 | Shye-Lin Wu | Method to fabricate short-channel MOSFETs with an improvement in ESD resistance |
JP4326606B2 (en) * | 1998-03-26 | 2009-09-09 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
JP2000040749A (en) * | 1998-07-24 | 2000-02-08 | Matsushita Electronics Industry Corp | Manufacture of semiconductor device |
JP2000150885A (en) * | 1998-09-07 | 2000-05-30 | Seiko Epson Corp | Method for setting threshold voltage of mos transistor and semiconductor device |
US20020036328A1 (en) * | 1998-11-16 | 2002-03-28 | William R. Richards, Jr. | Offset drain fermi-threshold field effect transistors |
US6297098B1 (en) * | 1999-11-01 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Tilt-angle ion implant to improve junction breakdown in flash memory application |
JP2001257343A (en) * | 2000-03-10 | 2001-09-21 | Hitachi Ltd | Semiconductor integrated circuit device |
JP2002026313A (en) * | 2000-07-06 | 2002-01-25 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method thereof |
JP2002198529A (en) * | 2000-10-18 | 2002-07-12 | Hitachi Ltd | Semiconductor device and its manufacturing method |
-
2001
- 2001-09-28 US US09/968,388 patent/US20030064550A1/en not_active Abandoned
-
2002
- 2002-08-22 TW TW091119022A patent/TW564487B/en not_active IP Right Cessation
- 2002-08-30 GB GB0220202A patent/GB2383189B/en not_active Expired - Fee Related
- 2002-09-26 JP JP2002280434A patent/JP4631097B2/en not_active Expired - Fee Related
- 2002-09-28 KR KR1020020059060A patent/KR100918182B1/en not_active IP Right Cessation
-
2003
- 2003-07-14 US US10/619,058 patent/US7049199B2/en not_active Expired - Lifetime
-
2010
- 2010-02-24 JP JP2010038787A patent/JP5762687B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB0220202D0 (en) | 2002-10-09 |
GB2383189A (en) | 2003-06-18 |
GB2383189B (en) | 2005-10-12 |
JP2010157759A (en) | 2010-07-15 |
TW564487B (en) | 2003-12-01 |
US20040014303A1 (en) | 2004-01-22 |
JP5762687B2 (en) | 2015-08-12 |
JP4631097B2 (en) | 2011-02-16 |
US7049199B2 (en) | 2006-05-23 |
KR100918182B1 (en) | 2009-09-22 |
JP2003178995A (en) | 2003-06-27 |
KR20030027843A (en) | 2003-04-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10032903B2 (en) | Threshold voltage adjustment of a transistor | |
US5548143A (en) | Metal oxide semiconductor transistor and a method for manufacturing the same | |
US5510279A (en) | Method of fabricating an asymmetric lightly doped drain transistor device | |
US6316302B1 (en) | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | |
US6255152B1 (en) | Method of fabricating CMOS using Si-B layer to form source/drain extension junction | |
US7393752B2 (en) | Semiconductor devices and method of fabrication | |
JP5762687B2 (en) | Ion implantation method to achieve desired dopant concentration | |
EP0814502A1 (en) | Complementary semiconductor device and method for producing the same | |
JP2000260987A (en) | Semiconductor device and its manufacture | |
US6709939B2 (en) | Method for fabricating semiconductor device | |
KR100391959B1 (en) | Semiconductor apparatus and method of manufacture | |
US6603179B2 (en) | Semiconductor apparatus including CMOS circuits and method for fabricating the same | |
US20040041170A1 (en) | Low dose super deep source/drain implant | |
KR100276744B1 (en) | Semiconductor device having LDD structure and manufacturing method thereof | |
US6008100A (en) | Metal-oxide semiconductor field effect transistor device fabrication process | |
US5623154A (en) | Semiconductor device having triple diffusion | |
US6576521B1 (en) | Method of forming semiconductor device with LDD structure | |
JP2790050B2 (en) | Method for manufacturing semiconductor device | |
US6544853B1 (en) | Reduction of negative bias temperature instability using fluorine implantation | |
US6624476B1 (en) | Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating | |
US7335549B2 (en) | Semiconductor device and method for fabricating the same | |
JP4548946B2 (en) | Manufacturing method of semiconductor device | |
GB2411292A (en) | Transistors with different threshold voltages and tub dopant profile | |
KR100334968B1 (en) | Method for fabricating buried channel type PMOS transistor | |
KR20010104013A (en) | MOS transistor for suppressing bulk punthrough |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: AGERE SYSTEMS GAURDIAN CORP., FLORIDA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LAYMAN, PAUL ARTHUR;CHAUDHRY, SAMIR;REEL/FRAME:012235/0484 Effective date: 20010926 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0001 Effective date: 20171208 |
|
AS | Assignment |
Owner name: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERA Free format text: SECURITY INTEREST;ASSIGNORS:HILCO PATENT ACQUISITION 56, LLC;BELL SEMICONDUCTOR, LLC;BELL NORTHERN RESEARCH, LLC;REEL/FRAME:045216/0020 Effective date: 20180124 |
|
AS | Assignment |
Owner name: BELL NORTHERN RESEARCH, LLC, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:060885/0001 Effective date: 20220401 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:060885/0001 Effective date: 20220401 Owner name: HILCO PATENT ACQUISITION 56, LLC, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:060885/0001 Effective date: 20220401 |