JP2004527126A5 - - Google Patents

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Publication number
JP2004527126A5
JP2004527126A5 JP2002584381A JP2002584381A JP2004527126A5 JP 2004527126 A5 JP2004527126 A5 JP 2004527126A5 JP 2002584381 A JP2002584381 A JP 2002584381A JP 2002584381 A JP2002584381 A JP 2002584381A JP 2004527126 A5 JP2004527126 A5 JP 2004527126A5
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JP
Japan
Prior art keywords
dielectric layer
forming
metal layer
dummy
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002584381A
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English (en)
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JP2004527126A (ja
Filing date
Publication date
Priority claimed from US10/108,614 external-priority patent/US6638863B2/en
Application filed filed Critical
Publication of JP2004527126A publication Critical patent/JP2004527126A/ja
Publication of JP2004527126A5 publication Critical patent/JP2004527126A5/ja
Pending legal-status Critical Current

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Claims (6)

  1. 金属層と誘電体層とを含み、前記誘電体層が、
    凹状領域及び非凹状領域のパターンであって、前記金属層が前記非凹状領域から電解研磨され、前記凹状領域を充填して複数の相互接続部を形成しているもの、及び
    前記誘電体層の前記非凹状領域に配置された複数のダミー構造
    を含んでなる、半導体構造体。
  2. 誘電体層と金属層とを含み、
    前記誘電体層が、複数のトレンチ及び複数のダミー構造を有し、ここで、前記複数のトレンチ及び前記複数のダミー構造が前記誘電体層によって分離されており、かつ
    前記金属層が前記トレンチを充填して金属製相互接続部を形成している、半導体構造体。
  3. 複数の半導体ダイと、該複数の半導体ダイに隣接して形成された複数のダミー構造とを含み、
    前記複数の半導体ダイが、
    複数のトレンチを備えた誘電体層、及び
    前記トレンチを充填して相互接続部を形成した金属層
    を含んでなる、半導体構造体。
  4. 半導体構造体を製造する方法であって、
    凹状領域及び非凹状領域を含む誘電体層を形成する段階と、
    前記非凹状領域内に複数のダミー構造を形成する段階と、
    前記誘電体層及び前記ダミー構造を覆うべく、金属層を形成する段階と、
    前記金属層を電解研磨して記非凹状領域を露出する段階と、
    含んでなる、半導体構造体の製造方法。
  5. 相互接続構造体を製造する方法であって、
    誘電体層を形成し、該誘電体層をパターニングして相互接続部を形成する段階と、
    前記相互接続部に隣接して複数のダミー構造を形成する段階と、
    前記パターニングされた誘電体層及び前記ダミー構造を覆うべく金属層を形成する段階と、
    前記金属層を電解研磨して前記相互接続部を分離する段階と、
    を含んでなる、相互接続構造体の製造方法。
  6. 半導体構造体を形成する方法であって、
    複数のダイを半導体ウェハ上に形成することを含み、かつ前記ダイのそれぞれを形成することが、
    凹状領域及び非凹状領域を有する誘電体層を形成する段階と、
    前記誘電体層の上に金属層を形成しかつ前記非凹状領域を充填する段階と、
    前記誘電体層の前記非凹状領域内に少なくとも一個のダミー構造を形成する段階と、
    前記金属層を電解研磨して前記非凹状領域を露出する段階と、
    を含んでなる、半導体構造体の形成方法。
JP2002584381A 2001-04-24 2002-04-04 ダミー構造を備えたトレンチもしくはバイアを有するウェハ上の金属層を電解研磨する方法 Pending JP2004527126A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US28627301P 2001-04-24 2001-04-24
US10/108,614 US6638863B2 (en) 2001-04-24 2002-03-27 Electropolishing metal layers on wafers having trenches or vias with dummy structures
PCT/US2002/010500 WO2002086961A1 (en) 2001-04-24 2002-04-04 Electropolishing metal layers on wafers having trenches or vias with dummy structures

Publications (2)

Publication Number Publication Date
JP2004527126A JP2004527126A (ja) 2004-09-02
JP2004527126A5 true JP2004527126A5 (ja) 2005-12-22

Family

ID=26806086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002584381A Pending JP2004527126A (ja) 2001-04-24 2002-04-04 ダミー構造を備えたトレンチもしくはバイアを有するウェハ上の金属層を電解研磨する方法

Country Status (7)

Country Link
US (2) US6638863B2 (ja)
EP (1) EP1382065A4 (ja)
JP (1) JP2004527126A (ja)
KR (1) KR101018187B1 (ja)
CN (1) CN100541746C (ja)
TW (1) TWI258814B (ja)
WO (1) WO2002086961A1 (ja)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6939795B2 (en) * 2002-09-23 2005-09-06 Texas Instruments Incorporated Selective dry etching of tantalum and tantalum nitride
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US20040182721A1 (en) * 2003-03-18 2004-09-23 Applied Materials, Inc. Process control in electro-chemical mechanical polishing
US6962524B2 (en) * 2000-02-17 2005-11-08 Applied Materials, Inc. Conductive polishing article for electrochemical mechanical polishing
US6848970B2 (en) * 2002-09-16 2005-02-01 Applied Materials, Inc. Process control in electrochemically assisted planarization
US6991526B2 (en) * 2002-09-16 2006-01-31 Applied Materials, Inc. Control of removal profile in electrochemically assisted CMP
US20040253809A1 (en) * 2001-08-18 2004-12-16 Yao Xiang Yu Forming a semiconductor structure using a combination of planarizing methods and electropolishing
US6837983B2 (en) * 2002-01-22 2005-01-04 Applied Materials, Inc. Endpoint detection for electro chemical mechanical polishing and electropolishing processes
KR20040097337A (ko) * 2002-04-12 2004-11-17 에이씨엠 리서치, 인코포레이티드 전해 연마 및 전기 도금 방법
WO2003098676A1 (en) * 2002-05-17 2003-11-27 Ebara Corporation Substrate processing apparatus and substrate processing method
KR100467803B1 (ko) * 2002-07-23 2005-01-24 동부아남반도체 주식회사 반도체 소자 제조 방법
US20050061674A1 (en) 2002-09-16 2005-03-24 Yan Wang Endpoint compensation in electroprocessing
US7112270B2 (en) * 2002-09-16 2006-09-26 Applied Materials, Inc. Algorithm for real-time process control of electro-polishing
US6812069B2 (en) * 2002-12-17 2004-11-02 Taiwan Semiconductor Manufacturing Co., Ltd Method for improving semiconductor process wafer CMP uniformity while avoiding fracture
JP2004273438A (ja) * 2003-02-17 2004-09-30 Pioneer Electronic Corp エッチング用マスク
US7042065B2 (en) * 2003-03-05 2006-05-09 Ricoh Company, Ltd. Semiconductor device and method of manufacturing the same
US6693357B1 (en) 2003-03-13 2004-02-17 Texas Instruments Incorporated Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
JP4575651B2 (ja) * 2003-06-04 2010-11-04 富士ゼロックス株式会社 積層構造体の製造方法および積層構造体
US7223685B2 (en) * 2003-06-23 2007-05-29 Intel Corporation Damascene fabrication with electrochemical layer removal
KR100546354B1 (ko) * 2003-07-28 2006-01-26 삼성전자주식회사 원하는 분석 위치를 용이하게 찾을 수 있는 반도체 소자
JP2005057003A (ja) * 2003-08-01 2005-03-03 Sanyo Electric Co Ltd 半導体集積回路装置
US6818517B1 (en) * 2003-08-29 2004-11-16 Asm International N.V. Methods of depositing two or more layers on a substrate in situ
US7071074B2 (en) * 2003-09-24 2006-07-04 Infineon Technologies Ag Structure and method for placement, sizing and shaping of dummy structures
US20080306126A1 (en) * 2004-01-05 2008-12-11 Fonseca Vivian A Peroxisome proliferator activated receptor treatment of hyperhomocysteinemia and its complications
KR100580110B1 (ko) * 2004-05-28 2006-05-12 매그나칩 반도체 유한회사 반도체 소자의 더미 패턴 구조
US7339272B2 (en) * 2004-06-14 2008-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with scattering bars adjacent conductive lines
JP2006173501A (ja) * 2004-12-17 2006-06-29 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7655565B2 (en) * 2005-01-26 2010-02-02 Applied Materials, Inc. Electroprocessing profile control
CN101142668A (zh) 2005-03-16 2008-03-12 富士通株式会社 半导体装置及其制造方法
KR100724191B1 (ko) * 2005-12-28 2007-05-31 동부일렉트로닉스 주식회사 반도체소자의 화학적기계 연마방법
US7422982B2 (en) * 2006-07-07 2008-09-09 Applied Materials, Inc. Method and apparatus for electroprocessing a substrate with edge profile control
JP5055980B2 (ja) * 2006-11-29 2012-10-24 富士通セミコンダクター株式会社 電子装置の製造方法および半導体装置の製造方法
KR100910447B1 (ko) * 2007-05-18 2009-08-04 주식회사 동부하이텍 금속 패드 형성 방법
US8957484B2 (en) * 2008-02-29 2015-02-17 University Of Washington Piezoelectric substrate, fabrication and related methods
KR101487370B1 (ko) * 2008-07-07 2015-01-30 삼성전자주식회사 마스크 레이아웃의 형성 방법 및 마스크 레이 아웃
JP5412517B2 (ja) * 2008-08-20 2014-02-12 エーシーエム リサーチ (シャンハイ) インコーポレーテッド バリア層除去方法及び装置
KR20100060309A (ko) * 2008-11-27 2010-06-07 주식회사 동부하이텍 반도체 소자
US8604898B2 (en) 2009-04-20 2013-12-10 International Business Machines Corporation Vertical integrated circuit switches, design structure and methods of fabricating same
JP5278549B2 (ja) * 2009-06-26 2013-09-04 株式会社Sumco シリコンウェーハの洗浄方法、およびその洗浄方法を用いたエピタキシャルウェーハの製造方法
US8432031B1 (en) * 2009-12-22 2013-04-30 Western Digital Technologies, Inc. Semiconductor die including a current routing line having non-metallic slots
US9443796B2 (en) * 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US8772951B1 (en) * 2013-08-29 2014-07-08 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
US9159670B2 (en) 2013-08-29 2015-10-13 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
CN103474393B (zh) * 2013-09-11 2015-07-08 华进半导体封装先导技术研发中心有限公司 免cmp的电镀面铜去除及阻挡层复用的工艺方法
CN104637862B (zh) * 2013-11-14 2019-10-18 盛美半导体设备(上海)有限公司 半导体结构形成方法
CN104793298B (zh) * 2015-04-13 2017-03-22 华进半导体封装先导技术研发中心有限公司 一种带侧面焊盘的载板结构及其制作方法
US10312141B2 (en) * 2016-08-16 2019-06-04 Northrop Grumman Systems Corporation Preclean methodology for superconductor interconnect fabrication
CN106803495B (zh) * 2016-12-28 2019-11-22 上海集成电路研发中心有限公司 金属埋层凸起的去除方法以及空气隙的制备方法
JP7353121B2 (ja) 2019-10-08 2023-09-29 キヤノン株式会社 半導体装置および機器
US11976002B2 (en) * 2021-01-05 2024-05-07 Applied Materials, Inc. Methods for encapsulating silver mirrors on optical structures

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4127459A (en) 1977-09-01 1978-11-28 Jumer John F Method and apparatus for incremental electro-polishing
US4190513A (en) 1978-09-18 1980-02-26 Jumer John F Apparatus for containerless portable electro-polishing
US5256565A (en) * 1989-05-08 1993-10-26 The United States Of America As Represented By The United States Department Of Energy Electrochemical planarization
JPH0438852A (ja) * 1990-06-04 1992-02-10 Hitachi Ltd 多層配線を有する半導体装置
US5486234A (en) * 1993-07-16 1996-01-23 The United States Of America As Represented By The United States Department Of Energy Removal of field and embedded metal by spin spray etching
JP3297220B2 (ja) * 1993-10-29 2002-07-02 株式会社東芝 半導体装置の製造方法および半導体装置
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
JPH08195393A (ja) * 1995-01-17 1996-07-30 Toshiba Corp メタル配線形成方法
JP3382467B2 (ja) * 1995-09-14 2003-03-04 キヤノン株式会社 アクティブマトリクス基板の製造方法
US6309956B1 (en) 1997-09-30 2001-10-30 Intel Corporation Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
US6045434A (en) 1997-11-10 2000-04-04 International Business Machines Corporation Method and apparatus of monitoring polishing pad wear during processing
US6395152B1 (en) * 1998-07-09 2002-05-28 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US6232231B1 (en) * 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6315883B1 (en) * 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
US6709565B2 (en) 1998-10-26 2004-03-23 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
US6413388B1 (en) 2000-02-23 2002-07-02 Nutool Inc. Pad designs and structures for a versatile materials processing apparatus
CN1264162A (zh) * 1999-02-13 2000-08-23 国际商业机器公司 用于铝化学抛光的虚拟图形
US6395607B1 (en) * 1999-06-09 2002-05-28 Alliedsignal Inc. Integrated circuit fabrication method for self-aligned copper diffusion barrier
JP2001044195A (ja) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6234870B1 (en) 1999-08-24 2001-05-22 International Business Machines Corporation Serial intelligent electro-chemical-mechanical wafer processor
JP4513145B2 (ja) * 1999-09-07 2010-07-28 ソニー株式会社 半導体装置の製造方法および研磨方法
US6653226B1 (en) * 2001-01-09 2003-11-25 Novellus Systems, Inc. Method for electrochemical planarization of metal surfaces
US6383917B1 (en) * 1999-10-21 2002-05-07 Intel Corporation Method for making integrated circuits
JP2002158278A (ja) 2000-11-20 2002-05-31 Hitachi Ltd 半導体装置およびその製造方法ならびに設計方法
US6627550B2 (en) * 2001-03-27 2003-09-30 Micron Technology, Inc. Post-planarization clean-up
US6852630B2 (en) 2001-04-23 2005-02-08 Asm Nutool, Inc. Electroetching process and system

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