KR100580110B1 - 반도체 소자의 더미 패턴 구조 - Google Patents
반도체 소자의 더미 패턴 구조 Download PDFInfo
- Publication number
- KR100580110B1 KR100580110B1 KR1020040038460A KR20040038460A KR100580110B1 KR 100580110 B1 KR100580110 B1 KR 100580110B1 KR 1020040038460 A KR1020040038460 A KR 1020040038460A KR 20040038460 A KR20040038460 A KR 20040038460A KR 100580110 B1 KR100580110 B1 KR 100580110B1
- Authority
- KR
- South Korea
- Prior art keywords
- dummy
- patterns
- dummy pattern
- dummy patterns
- pattern
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 238000001465 metallisation Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 3
- 230000032798 delamination Effects 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 20
- 238000007517 polishing process Methods 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000002474 experimental method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000007261 regionalization Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006471 dimerization reaction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (17)
- 금속배선이 형성되는 층간 절연막에서 금속배선이 형성되지 않는 지역에 다각형의 각 꼭지점에 해당하는 부분에 각각 형성되어 다각형 형태를 이루면서 상기 지역 전반에 걸쳐 배열된 자 더미 패턴들;상기 자 더미 패턴들에 의해 형태를 이루는 상기 다각형의 가운데에 해당하는 부분에 각각 형성되는 모 더미 패턴들로 구성된 반도체 소자의 더미 패턴 구조.
- 삭제
- 제 1 항에 있어서,상기 자 더미 패턴들 및 상기 모 더미 패턴들은 상기 금속배선을 형성하는 공정과 동일한 공정으로 형성되는 반도체 소자의 더미 패턴 구조.
- 제 3 항에 있어서,상기 자 더미 패턴들, 상기 모 더미 패턴들 및 상기 금속배선은 다마신 공정을 사용하여 형성되는 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 자 더미 패턴들은 삼각형, 사각형, 오각형, 육각형 및 팔각형 중 어느 하나의 형태로 배열되는 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 자 더미 패턴들은 정사각형, 정오각형, 정육각형 및 정팔각형 중 어느 하나의 형태로 배열하는 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 자 더미 패턴들 간의 거리는 3 내지 100 ㎛인 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 자 더미 패턴과 상기 모 더미 패턴 간의 거리는 3 내지 100 ㎛인 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 자 더미 패턴들 및 상기 모 더미 패턴들 각각은 다양한 다각형 모양으로 형성하되, 상기 다양한 다각형 중 동일한 다각형으로 형성되거나, 상기 다양한 다각형들이 혼합되어 형성된 반도체 소자의 더미 패턴 구조.
- 제 9 항에 있어서,상기 자 더미 패턴들 및 상기 모 더미 패턴들 각각은 상기 다각형의 한 변의 길이가 3 내지 100㎛인 반도체 소자의 더미 패턴 구조.
- 제 9 항에 있어서,상기 자 더미 패턴들 및 상기 모 더미 패턴들 각각은 면적이 9 내지 10000㎛2인 반도체 소자의 더미 패턴 구조.
- 제 9 항에 있어서,상기 자 더미 패턴 및 상기 모 더미 패턴은 다각형의 면적을 동일하게 형성하거나, 모 더미 패턴을 자 더미 패턴의 면적보다 크게 형성하거나, 자 더미 패턴을 모 더미 패턴의 면적보다 크게 형성하는 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 모 더미 패턴들 및 상기 자 더미 패턴들은 이들이 형성되는 전체 지역에서 10 내지 50%의 밀집도로 형성되는 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 모 더미 패턴들 및 상기 자 더미 패턴들은 금속배선이 형성되는 지역의 금속배선의 밀집도와 동일하거나 15% 이내로 높게 형성되는 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 모 더미 패턴들 및 상기 자 더미 패턴들이 형성되는 지역의 면적은 250000㎛2 이하인 반도체 소자의 더미 패턴 구조.
- 제 1 항에 있어서,상기 모 더미 패턴들 및 상기 자 더미 패턴들이 형성되는 지역의 면적이 250000㎛2 이상인 경우에는 더미 패턴의 면적보다 큰 면적의 패드 패턴들을 더 형성하는 것을 포함하는 반도체 소자의 더미 패턴 구조.
- 제 16 항에 있어서,상기 패드 패턴들은 10 내지 40% 밀집도로 형성되는 반도체 소자의 더미 패턴 구조.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040038460A KR100580110B1 (ko) | 2004-05-28 | 2004-05-28 | 반도체 소자의 더미 패턴 구조 |
US11/132,597 US7105927B2 (en) | 2004-05-28 | 2005-05-19 | Structure of dummy pattern in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040038460A KR100580110B1 (ko) | 2004-05-28 | 2004-05-28 | 반도체 소자의 더미 패턴 구조 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050112983A KR20050112983A (ko) | 2005-12-01 |
KR100580110B1 true KR100580110B1 (ko) | 2006-05-12 |
Family
ID=35424285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020040038460A KR100580110B1 (ko) | 2004-05-28 | 2004-05-28 | 반도체 소자의 더미 패턴 구조 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7105927B2 (ko) |
KR (1) | KR100580110B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101102295B1 (ko) * | 2008-10-30 | 2012-01-03 | 엘피다 메모리 가부시키가이샤 | 반도체 디바이스 및 그 제조 방법 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010087195A (ja) * | 2008-09-30 | 2010-04-15 | Panasonic Corp | 半導体装置 |
JP7567490B2 (ja) | 2021-01-14 | 2024-10-16 | Toppanホールディングス株式会社 | 配線基板及びその製造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5430325A (en) * | 1992-06-30 | 1995-07-04 | Rohm Co. Ltd. | Semiconductor chip having dummy pattern |
US5714784A (en) * | 1995-10-19 | 1998-02-03 | Winbond Electronics Corporation | Electrostatic discharge protection device |
US5838050A (en) * | 1996-06-19 | 1998-11-17 | Winbond Electronics Corp. | Hexagon CMOS device |
US5911110A (en) * | 1997-10-28 | 1999-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming shallow trench isolation with dummy pattern in reverse tone mask |
TW428243B (en) * | 1999-01-22 | 2001-04-01 | United Microelectronics Corp | Method for enhancing the planarization of the die region and scribe line by using dummy pattern |
JP2001168093A (ja) * | 1999-12-09 | 2001-06-22 | Sharp Corp | 半導体装置 |
US6563148B2 (en) * | 2000-04-19 | 2003-05-13 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with dummy patterns |
KR100500934B1 (ko) * | 2000-05-31 | 2005-07-14 | 주식회사 하이닉스반도체 | 웨이퍼 가장자리의 과도 연마를 방지할 수 있는 반도체소자 제조 방법 |
JP2002289839A (ja) * | 2001-03-26 | 2002-10-04 | Toshiba Corp | 半導体装置 |
JP3479052B2 (ja) * | 2001-04-23 | 2003-12-15 | 沖電気工業株式会社 | 半導体装置のダミー配置判定方法 |
US6638863B2 (en) * | 2001-04-24 | 2003-10-28 | Acm Research, Inc. | Electropolishing metal layers on wafers having trenches or vias with dummy structures |
JP2002373896A (ja) * | 2001-06-15 | 2002-12-26 | Mitsubishi Electric Corp | 半導体装置 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
JP2004104102A (ja) * | 2002-08-21 | 2004-04-02 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US6812069B2 (en) * | 2002-12-17 | 2004-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for improving semiconductor process wafer CMP uniformity while avoiding fracture |
JP2004281473A (ja) * | 2003-03-12 | 2004-10-07 | Kyocera Corp | 配線基板 |
US7071074B2 (en) * | 2003-09-24 | 2006-07-04 | Infineon Technologies Ag | Structure and method for placement, sizing and shaping of dummy structures |
-
2004
- 2004-05-28 KR KR1020040038460A patent/KR100580110B1/ko active IP Right Grant
-
2005
- 2005-05-19 US US11/132,597 patent/US7105927B2/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101102295B1 (ko) * | 2008-10-30 | 2012-01-03 | 엘피다 메모리 가부시키가이샤 | 반도체 디바이스 및 그 제조 방법 |
US8502384B2 (en) | 2008-10-30 | 2013-08-06 | Elpida Memory, Inc. | Semiconductor device and manufacturing method thereof |
US8736063B2 (en) | 2008-10-30 | 2014-05-27 | Elpida Memory, Inc. | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR20050112983A (ko) | 2005-12-01 |
US20050263904A1 (en) | 2005-12-01 |
US7105927B2 (en) | 2006-09-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7741715B2 (en) | Crack stop and moisture barrier | |
US7466028B1 (en) | Semiconductor contact structure | |
US8237272B2 (en) | Conductive pillar structure for semiconductor substrate and method of manufacture | |
US20060186537A1 (en) | Delamination reduction between vias and conductive pads | |
US6791196B2 (en) | Semiconductor devices with bonding pads having intermetal dielectric layer of hybrid configuration and methods of fabricating the same | |
KR101353343B1 (ko) | 활성 영역 상에서 비트라인 패턴의 일 측부로부터 서로다른 거리들로 각각 이격되는 스토리지 노드들을 가지는반도체 장치들 및 그 형성방법들 | |
CN111512431B (zh) | 用于预防焊料桥接的互连结构及相关系统及方法 | |
JP2008252042A (ja) | 回路基板、および回路基板の形成方法 | |
US8288270B2 (en) | Enhanced electromigration resistance in TSV structure and design | |
JP6142499B2 (ja) | 配線構造及びその製造方法 | |
CN113871312A (zh) | 具有牺牲柱的半导体装置组合件和制造牺牲柱的方法 | |
JP3645129B2 (ja) | 半導体装置の製造方法 | |
KR100580110B1 (ko) | 반도체 소자의 더미 패턴 구조 | |
CN100481416C (zh) | 半导体装置和层叠型半导体装置以及它们的制造方法 | |
US20060223304A1 (en) | Semiconductor device and pattern generating method | |
TWI548094B (zh) | 半導體構造及形成半導體構造之方法 | |
US8421208B2 (en) | Electrode pad having a recessed portion | |
EP0982774A2 (en) | Avoidance of cross-sectional surface reduction in wide soft metal wires | |
US6094812A (en) | Dishing avoidance in wide soft metal wires | |
US6621167B1 (en) | Metal interconnect structure | |
KR20170033964A (ko) | 재배선 패드를 갖는 반도체 소자 | |
JP2005072403A (ja) | 半導体装置および半導体装置の製造方法 | |
US20090206451A1 (en) | Semiconductor device | |
US8957523B2 (en) | Dielectric posts in metal layers | |
EP4254470A1 (en) | Semiconductor product and method for manufacturing a semiconductor product |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130422 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20140421 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20150416 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20160418 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20170418 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20180418 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20190417 Year of fee payment: 14 |