CN111512431B - 用于预防焊料桥接的互连结构及相关系统及方法 - Google Patents

用于预防焊料桥接的互连结构及相关系统及方法 Download PDF

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CN111512431B
CN111512431B CN201880083258.9A CN201880083258A CN111512431B CN 111512431 B CN111512431 B CN 111512431B CN 201880083258 A CN201880083258 A CN 201880083258A CN 111512431 B CN111512431 B CN 111512431B
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interconnect structure
semiconductor die
top surface
conductive
barrier layer
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CN111512431A (zh
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K·S·迈尔
O·R·费伊
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本文中揭示其上形成有互连结构的半导体裸片及相关系统及方法。在一个实施例中，互连结构包含电耦合到半导体裸片的导电接点的导电材料。所述导电材料包含与所述导电接点垂直对准的第一部分，及横向延伸远离所述导电接点的第二部分。焊料材料安置于所述互连结构的所述第二部分上使得所述焊料材料至少部分横向偏离所述半导体裸片的所述导电接点。在一些实施例中，互连结构可进一步包含在回流工艺期间预防所述焊料材料的芯吸或其它非所要移动的围阻层。

Description

用于预防焊料桥接的互连结构及相关系统及方法
技术领域
本发明技术大体上涉及半导体装置，且在数个实施例中更特定来说，涉及用于裸片间及/或封装间互连的互连结构。
背景技术
例如存储器装置、微处理器及发光二极管的微电子装置通常包含安装到衬底且围封于保护层中的一或多个半导体裸片。半导体裸片包含功能特征，例如存储器单元、处理器电路、互连电路等。半导体裸片制造商面临越来越大的压力，既减小由半导体裸片占用的体积又增大所得囊封组合件的容量及/或速度。为满足这些需求，半导体裸片制造商通常将多个半导体裸片垂直地堆叠于彼此的顶部上以增大电路板上的有限体积内的微电子装置或半导体裸片所安装到的其它元件的容量或性能。
堆叠的半导体裸片通常通过附接到形成于裸片的接合垫上的金属柱的焊料凸块电连接。每一半导体裸片的接合垫通常紧密地间隔在一起使得当焊料在堆叠过程期间回流以形成焊料凸块时，焊料有时可“桥接”在相邻金属柱之间以电连接柱的相邻柱且使半导体装置短路。用于抑制焊料桥接的常规方法包含通过在半导体裸片上形成重布层(RDL)而放松柱间距以将电连接重新分配到接合垫。替代地，半导体裸片可经重新设计使得每一裸片的接合垫具有更大间距。然而，这些方法两者可增加设计及制造半导体装置的成本及/或复杂性。
附图说明
图1A是具有根据本发明技术的实施例配置的互连结构的半导体裸片的俯视平面图。
图1B是展示根据本发明技术的实施例的个别互连结构的图1A的半导体裸片的放大横截面视图。
图2A到2G是说明根据本发明技术的实施例的用于制造互连结构的方法中的各个阶段的半导体裸片的放大横截面视图。
图3A到3D是说明根据本发明技术的实施例的用于制造互连结构的方法中的各个阶段的半导体裸片的放大横截面视图。
图4是包含根据本发明技术的实施例配置的半导体裸片的系统的示意图。
具体实施方式
在下文中描述半导体装置的数个实施例的具体细节以及相关系统及方法。半导体装置的实例包含逻辑装置、存储器装置、微处理器及二极管等等。术语“半导体装置”可指代完成装置或指代处于成为完成装置之前的各个处理阶段的组合件或其它结构。取决于使用术语“衬底”的上下文，术语“衬底”可指代晶片级衬底或指代单粒化裸片级衬底。相关领域的一般技术人员将认识到，可在晶片级或在裸片级执行本文中描述的方法的适合步骤。此外，除非上下文另有指示，否则可使用常规半导体制造技术来形成本文中揭示的结构。可(举例来说)使用化学气相沉积、物理气相沉积、原子层沉积、旋涂及/或其它适合技术来沉积材料。类似地，可(举例来说)使用等离子体蚀刻、湿式蚀刻、化学机械平坦化或其它适合技术来移除材料。
在下文中描述的数个实施例中，半导体裸片包含半导体衬底，其具有暴露在半导体衬底的表面处的至少一第一接点及第二接点(例如，接合垫或延伸穿过衬底的通孔的部分)。第一互连结构电耦合到第一接点，且第二互连结构电耦合到第二接点。第一互连结构可包含具有第一接点上方的第一部分及横向偏离第一接点的第二部分的顶部表面。焊料材料可安置于顶部表面的第二部分上使得焊料材料至少部分横向偏离第一接点。类似地，第二互连结构可包含具有第二接点上方的第三部分及横向偏离第二接点的第四部分的顶部表面，且焊料材料可安置于顶部表面的第四部分上使得焊料材料至少部分偏离第二接点。
在某些实施例中，第一互连结构与第二互连结构上的焊料材料之间的距离大于第一接点与第二接点之间的距离。因此，相较于其中焊料材料与半导体裸片的接点垂直地对准的常规互连结构，本发明技术的互连结构可降低焊料材料在焊料材料的回流期间桥接于第一互连结构与第二互连结构之间的可能性。此预期通过减少经制造半导体装置的焊料桥接及因此电短路的发生而增大良率。
如本文中使用，术语“垂直”、“横向”、“上”及“下”可指代半导体装置中的特征鉴于图中展示的定向的相对方向或位置。举例来说，“上”或“最上”可指代与另一特征相比，定位为更接近页面的顶部的特征。然而，这些术语应广泛解释为包含具有其它定向(例如颠倒或倾斜定向)的半导体装置，其中顶部/底部、上方/下方、之上/之下、上/下及左/右可取决于定向而互换。此外，为便于参考，贯穿本发明使用相同元件符号来识别类似或相似组件或特征，但相同元件符号的使用不暗示特征应解释为相同的。实际上，在本文中描述的许多实例中，相同编号特征具有在结构及/或功能方面彼此相异的多个实施例。此外，可使用相同阴影来指示可在组成上类似的横截面中的材料，但相同阴影的使用不暗示材料应解释为相同，除非本文中明确说明。
图1A是具有根据本发明技术的实施例配置的互连结构110的半导体裸片100的俯视平面图。图1B是图1A的半导体裸片100的部分的放大横截面视图，其展示根据本发明技术的实施例配置的个别互连结构110。一起参考图1A及1B，半导体裸片100包含具有上表面103及至少部分在上表面103上方的绝缘材料104的衬底102(例如，半导体衬底)。绝缘材料104可为(举例来说)适合电介质材料(例如，钝化材料、聚酰亚胺材料及/或用于覆盖半导体装置的顶部表面的其它材料)。半导体裸片100进一步包含在衬底102的上表面103处且至少部分通过绝缘材料104中的开口107从绝缘材料104暴露的导电接点106(图1A中以虚线展示)。互连结构110电耦合到对应接点106，且电连接体130(例如，焊料球、微型凸块等)可安置于互连结构110中的每一者上。
一般来说，接点106电耦合到衬底102的集成电路。集成电路可包含(举例来说)存储器电路(例如，动态随机存储器(DRAM))、控制器电路(例如，DRAM控制器)、逻辑电路及/或其它电路或电路的组合。在一些实施例中，接点106是接合垫，而在其它实施例中，接点106可为部分或完全延伸穿过衬底102的通孔(例如，硅穿孔(TSV))的部分。举例来说，如图1B中展示，接点106可为完全延伸穿过衬底102的TSV 109(图1B中以虚线展示)的上部。在一些实施例中，TSV 109包含电介质衬层及电介质衬层内的导电插塞。
在图1A中说明的实施例中，衬底102具有大体上矩形形状，而在其它实施例中，衬底102可具有任何其它形状，例如圆形、方形、多边形等。如展示，接点106可各自具有直线(例如，方形)形状且可沿着衬底102的上表面103布置成两列。然而，在其它实施例中，接点106可具有任何其它形状、配置或数目。举例来说，接点106可为圆形、多边形等，且可布置成沿着上表面103定位的多个行及/或列。同样地，每一行及/或每一列可具有多于或少于说明的六个接点106。此外，如图1A中展示，接点106中的每一者与相同列中的接点106的相邻者相等地间隔距离D1。在某些实施例中，相邻接点106之间的距离可改变。
参考图1B，互连结构110各自包含第一导电材料112及安置于第一导电材料112上方的第二导电材料114。第一导电材料112定位于对应接点106的至少一部分上方以将互连结构110电耦合到接点106。第一导电材料112在绝缘材料104上方从接点106横向向外延伸(例如，在图1B中说明的实施例中延伸到页面的右侧)。第二导电材料114界定互连结构110的顶部表面122，且第一导电材料112及第二导电材料114(统称为“导电材料112、114”)共同界定延伸在顶部表面122与绝缘材料104及接点106之间的互连结构110的侧壁表面124。更特定来说，如图1A及1B两者中展示，互连结构110的顶部表面122可各自具有与对应接点106垂直地对准(例如，重叠)的第一部分113a及横向偏离接点106且因此未与接点106垂直地对准的第二部分113b。
在图1A及1B中说明的实施例中，互连结构110具有细长(大体上直线)形状。然而，互连结构110的形状及尺寸可改变。举例来说，在一些实施例中，互连结构110可具有其它横截面形状，例如矩形、规则多边形、不规则多边形、椭圆等。此外，在一些实施例中，互连结构110可具有介于约100纳米到100微米之间(例如，约4到50微米)的高度。在某些实施例中，互连结构110可横向延伸远离接点106介于约1到3000微米之间(例如，约100微米、约150微米、约200微米等)的距离。即，互连结构110的顶部表面122的第二部分113b可具有介于约1到3000微米之间的长度。在一些实施例中，互连结构110可横向延伸到接近半导体裸片100的边缘。在特定实施例中，第一导电材料112包括铜且第二导电材料114包括镍。在其它实施例中，导电材料112、114可包括任何导电材料，例如(举例来说)金、硅、钨等。在又其它实施例中，互连结构110可包含仅单个导电材料，或相同或不同导电材料的两个以上层。
电连接体130至少部分安置于第二部分113b上使得电连接体130至少部分横向偏离接点106。如图1A及1B中展示，电连接体130可完全安置于顶部表面122的第二部分113b内使得电连接体130未与接点106垂直地对准。在其它实施例中，电连接体130中的一或多者可部分安置于第一部分113a及第二部分113b内(例如，横跨第一部分113a及第二部分113b)。因此，在一些实施例中，电连接体130中的一或多者的一部分(例如，小于约25％、小于约50％、小于约75％等)可与对应接点106垂直地对准(例如，重叠)。在一些实施例中，多个电连接体130可安置于相同互连结构110上。电连接体130可包括焊料材料，例如(举例来说)锡-银、铟或用于在互连结构110与相邻半导体裸片或其它电装置(例如，衬底、半导体封装等)之间形成电及机械连接的适合焊料材料。
再次参考图1B，每一互连结构110可进一步包含至少部分在顶部表面122的第一部分113a上方的围阻层116。在一些实施例中，如图1B中展示，围阻层116可形成在导电材料112、114的全部或基本上全部暴露部分上方。更特定来说，在某些实施例中，围阻层116可形成在互连结构110的全部侧壁表面124上方、顶部表面122的整个第一部分113a上方且部分在顶部表面122的第二部分113b上方，其中电连接体130未接触第二导电材料114。在其它实施例中，围阻层116可形成在或多或少的顶部表面122及侧壁表面124上方。举例来说，在一些实施例中，围阻层116未形成在互连结构110的侧壁表面122上方。
一般来说，围阻层116经配置以限制电连接体130(例如，焊料材料)且在(举例来说)回流工艺期间抑制将电连接体130芯吸到互连结构110的非所要表面上。此芯吸可通过使由电连接体130形成的接点的整体导电性及机械强度而有害地影响互连结构110与(举例来说)另一半导体裸片之间的电及/或机械连接。如图1B中展示，围阻层116可抑制电连接体130(i)从第二部分113b到顶部表面122的第一部分113a上及/或朝向第一部分113a及(ii)从第二部分113b到侧壁表面124上及/或朝向侧壁表面124的芯吸。在一些实施例中，围阻层116包括预防将电连接体130润湿到其所覆盖的导电材料112、114的表面上的防润湿材料。即，围阻层116的防润湿材料可为电连接体130提供不可润湿表面。举例来说，围阻层116的防润湿材料可具有电连接体130的可扩散性，其是极低或可忽略的。在一些实施例中，围阻层116包括氧化物、氮化物或聚酰亚胺。在特定实施例中，围阻层116包括氧化镍。在某些实施例中，围阻层116具有介于约100到之间，或在一些实施例中介于约2000到/>之间的厚度。在其中围阻层116包括聚酰亚胺的某些实施例中，围阻层116可具有介于约1到10微米之间(例如，约5微米)的厚度。
参考图1A的俯视平面图，在一些实施例中，相邻互连结构110(例如，电耦合到相同列中的接点106的相邻者的互连结构110)可在不同方向上沿着绝缘材料104横向延伸以增加电连接体130之间的间隔(例如，间距)。举例来说，如展示，电连接体130可通过大于相邻接点106之间的距离D1的距离D2分离。在某些实施例中，距离D2是第一距离D1的至少两倍。相比之下，常规互连结构在半导体裸片的接点上方垂直地延伸使得每一互连结构上的焊料与接点垂直地对准。因此，在此类常规装置中，焊料接点之间的间隔近似等于接点之间的间隔(例如，距离D1)。本文中描述的互连结构110有利地增加焊料接点之间的间隔以降低焊料材料在回流工艺期间桥接于互连结构110中的任一者之间且借此形成使半导体裸片100短路的电连接的可能性。因此，本发明技术可通过减少归因于焊料桥接的缺陷而增大半导体装置制造过程的良率。
图2A到2G是说明根据本发明技术的实施例的制造其上具有互连结构110的半导体裸片100的方法中的各个阶段的放大横截面视图。为便于解释及理解，图2A到2G说明半导体裸片100的单个互连结构110的制造。然而，关于图2A到2G说明的阶段可重复及/或扩展以形成半导体裸片100的互连结构110中的每一者。此外，一般来说，半导体裸片100可制造(举例来说)为离散装置或较大晶片或面板的部分。在晶片级或面板级制造中，较大半导体装置在经单粒化以形成多个个别半导体裸片之前形成。所属领域的技术人员将容易理解，半导体裸片100的制造可按比例调整为晶片及/或面板级，即，包含更多组件以便能够单粒化为一个以上半导体裸片100，同时包含与本文中描述类似的特征且使用类似过程。
参考图2A，在方法的此阶段，在绝缘材料104上形成第一掩模240(例如，光掩模)。第一掩模240可是具有至少部分与(i)绝缘材料104中的开口107、(ii)接点106及(iii)邻近接点106横向延伸的绝缘材料104的一部分对准的开口242的抗蚀剂材料或其它适合掩模材料。如下文中更详细地说明，互连结构110的导电部分经形成于第一掩模240的开口242中。在图2A中说明的实施例中，第一掩模240的开口242具有大体上矩形横截面形状。然而，可使用具有其它横截面形状的掩模来形成具有不同形状的互连结构。
在一些实施例中，半导体裸片100进一步具有形成于绝缘材料104及暴露于绝缘材料104的开口107处的接点106的部分上的籽晶结构(未描绘)。籽晶结构可为适于镀覆互连结构的基底或第一材料的单个材料。在一些实施例中，籽晶结构可包含势垒材料及所述势垒材料上的籽晶材料。势垒材料可为钽、氮化钽、钛、钛钨或预防互连结构材料扩散到绝缘材料104及衬底102中的另一材料。籽晶材料可为铜、铜合金、镍或用于使用所属领域中已知的电镀或无电式电镀技术来将第一导电材料112(图1B)镀覆到籽晶材料上的其它适合材料。举例来说，在一些实施例中，籽晶结构可包含使用物理气相沉积过程沉积的铜籽晶材料。
图2B说明在第一掩模240的开口242中以及接点106及绝缘材料104上方形成第一导电材料112之后的半导体裸片100。可使用所属领域中已知的电镀或无电式电镀工艺在开口242中形成第一导电材料112。在某些实施例中，第一材料112包括铜。
参考图2C，半导体裸片100的制造通过在第一掩模240的开口242(图2B)中及第一导电材料112上方形成第二导电材料114而继续。第二导电材料114可以与第一导电材料112相同或类似的方式形成，且可包括镍或其它适合材料。在一些实施例中，第二导电材料114可经选择以提供良好润湿表面用于在第二导电材料114上形成电连接体。
图2D说明在移除第一掩模240之后且在互连结构110的顶部表面122及侧壁表面124上方形成围阻层116之后的半导体裸片100。可使用湿式光致抗蚀剂剥除或所属领域中已知的其它适合技术来移除第一掩模240。在图2D中说明的实施例中，围阻层116经形成为导电材料112、114的全部暴露表面上方的毯覆层，包含覆盖整个顶部表面122。如上文中描述，围阻层可为(i)电连接体130(图1B)的焊料材料不容易在液相中润湿(例如，覆盖)到及/或(ii)具有针对电连接体130的焊料材料的低或可忽略可扩散性的材料。
在一些实施例中，通过将导电材料112、114暴露于等离子体(例如，使用等离子体增强化学气相沉积或其它适合工艺)而形成围阻层116。举例来说，在一些实施例中，等离子体是O2等离子体且第二导电材料114为镍。因此，围阻层116可至少部分包括氧化镍(例如，在互连结构110的顶部表面122处，其中O2等离子体与第二导电材料114反应)。在某些实施例中，在形成围阻层116之前未移除第一掩模240。在此类实施例中，围阻层116可仅形成在互连结构110的顶部表面122上，而不形成在侧壁表面124上。在其它实施例中，围阻层116可选择性地仅形成在顶部表面122及/或侧壁表面124的一部分上。在又其它实施例中，如下文中参考图3A到3D描述，可在形成围阻层116之前形成电连接体130。
参考图2E，半导体裸片100的制造通过至少在互连结构110的顶部表面122上的围阻层116上形成第二掩模250(例如，光掩模)而继续。第二掩模250可是具有至少部分与围阻层116的一部分对准的开口252的抗蚀剂材料或其它适合掩模材料。在其中在形成围阻层116之前未移除第一掩模240的一些实施例中，第二掩模250可至少部分形成于第一掩模240上方。如图2E中进一步说明，方法通过移除暴露于第二掩模250的开口252中的围阻层116的部分而继续。可使用(举例来说)氯化氢(HCl)清洁工艺、湿式清洁工艺、蚀刻工艺或所属领域中已知的另一工艺来移除围阻层116的部分。如图2E中展示，在移除围阻层116的部分之后，第二导电材料114暴露于第二掩模250的开口252中。在其它实施例中，代替使用光掩模，可使用标定激光器或另一适合工艺来移除围阻层116的一部分以暴露第二导电材料114的一部分。
图2F说明在第二掩模250的开口252(图2E)中形成电连接体130之后的半导体裸片100。举例来说，电连接体130可包括镀覆到第二掩模250的开口252中且镀覆到第二导电材料114的暴露部分上的焊料材料(例如，锡-银、铟焊料等)。也可通过将预成形焊料球安置于第二导电材料114上的适当位置中或通过使用适合网版印刷过程而形成电连接体130，如所属领域中已知。因此，电连接体130经由导电材料112、114电耦合到接点106及衬底102的集成电路。如图2F中展示，电连接体130在其形成于开口252中之后最初可具有直线(例如，块状)形状。
参考图2G，半导体裸片100的制造通过移除第二掩模250(图2F)且使电连接体130回流(例如，以形成焊料球或焊料凸块)(其给予电连接体130更圆形状)而继续。第二掩模250可以与第一掩模240相同或类似的方式(例如(举例来说)使用湿式光致抗蚀剂剥除或其它类似技术)移除。回流工艺可为所属领域中已知用于加热电连接体130以促成在互连件110与相邻半导体裸片或其它电组件之间形成电及/或机械连接的任何适合工艺。
图3A到3D是说明根据本发明技术的另一实施例的制造其上具有互连结构110的半导体裸片100的方法中的各个阶段的放大横截面视图。许多步骤可大体上类似于上文中参考图2A到2G描述的步骤。举例来说，图3A说明在第一掩模240已形成于绝缘材料104上之后且在将导电材料112、114镀覆到第一掩模240的开口中之后的半导体裸片100。然而，如图3A的实施例中进一步说明，第二掩模360(例如，光掩模)至少部分形成于第一掩模240及第二导电材料114上方。第二掩模360可是具有至少部分与第二导电材料114的一部分对准的开口362的抗蚀剂材料或其它适合掩模材料。
图3B说明在第二掩模360的开口362(图3A)中形成电连接体130之后且在移除第一掩模240及第二掩模360之后的半导体裸片100。电连接体130可为镀覆到暴露于开口362中的第二导电材料114的部分上的焊料材料(例如，锡-银)。也可通过将预成形焊料球安置于第二导电材料114上的适当位置中或通过使用适合网版印刷工艺而形成电连接体130，如所属领域中已知。可使用湿式光致抗蚀剂剥除或所属领域中已知的其它适合技术来移除第一掩模240及第二掩模360。应注意，在形成围阻层之前形成电连接体130。
参考图3C，半导体裸片100的制造通过在导电材料112、114及电连接体130的暴露部分上方形成围阻层116而继续。即，围阻层116经形成为互连结构110的整个侧壁表面124、互连结构110的顶部表面122的暴露部分及电连接体130的顶部及侧壁表面上方的毯覆层。在一些实施例中，通过将导电材料112、114及电连接体130暴露于等离子体(例如，使用等离子体增强化学气相沉积或其它适合工艺)而形成围阻层116。在某些实施例中，在形成电连接体130之后仅移除第二掩模360(图3A)，且在形成围阻层116之前未移除第一掩模240。在此类实施例中，围阻层116可仅形成在互连结构110的顶部表面122的暴露部分上，而不形成在侧壁表面124上。在其它实施例中，围阻层116可选择性地仅形成在顶部表面122及/或侧壁表面124的一部分上。
参考图3D，半导体裸片100的制造通过使电连接体130回流以在互连结构110的顶部表面122上形成(举例来说)通过导电材料112、114电耦合到接点106的焊料球或焊料凸块而继续。如图3D的实施例中说明，使电连接体130回流可从电连接体130的表面部分或完全移除围阻层116。举例来说，在一些实施例中，电连接体130可包括焊料材料及助熔剂材料。在回流工艺期间加热电连接体130可活化助熔剂材料以从电连接体130的表面移除围阻层116(例如，氧化物)。在其它实施例中，液体助熔剂可在回流工艺之前或期间引入到电连接体130以促成电连接体130的表面上的围阻层116的移除。回流工艺可为所属领域中已知用于加热电连接体130以促成与相邻半导体裸片或另一电组件形成电及/或机械连接的任何适合工艺。
应注意，可在不增加用于形成互连结构的现存方法的显著额外成本或复杂性的情况下形成互连结构110。举例来说，相较于用于形成与半导体裸片的接点垂直地对准的互连结构的许多常规方法，上文中参考图2A到3D描述的方法仅并入(i)用于镀覆导电材料的掩模图案的变化(例如，使得导电材料112、114横向延伸远离对应接点106以形成细长互连结构110)及(ii)形成预防焊料材料沿着细长互连结构芯吸的围阻层的额外步骤。特定来说，预期对用于形成互连结构的现存过程的这些修改不如增加半导体装置中的焊点之间的间隔的其它方法(例如在半导体裸片上形成重布层(RDL)或重新设计半导体裸片自身)复杂。
具有上文中参考图1A到3D描述的特征的半导体裸片的任一者可并入到大量更大及/或更复杂系统中的任一者中，系统的代表性实例是图4中示意性地展示的系统400。系统400可包含处理器402、存储器404(例如，SRAM、DRAM、快闪及/或其它存储器装置)、输入/输出装置405及/或其它子系统或组件408。上文中参考图1A到3D描述的半导体裸片可包含于图4中展示的元件中的任一者中。所得系统400可经配置以执行广泛多种适合计算、处理、存储、感测、成像及/或其它功能中的任一者。因此，系统400的代表性实例包含(而不限于)计算机及/或其它数据处理器，例如桌面计算机、膝上型计算机、因特网设备、手持式装置(例如，掌上计算机、穿戴式计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器系统、基于处理器或可编程消费型电子器件、网络计算机及微型计算机。系统400的额外代表性实例包含灯、相机、运载工具等。关于这些及其它实例，系统400可容置于单个单元中或分布于多个互连单元(例如，通过通信网络)上。系统400的组件可因此包含本地及/或远程存储器存储装置及广泛多种适合计算机可读媒体中的任一者。
从前述内容，将了解，本文中已出于说明的目的描述本发明的特定实施例，但可作出各种修改而不偏离本发明。因此，本发明除如通过所附权利要求书限制外并不受限。此外，在其它实施例中也可组合或消除在特定实施例的上下文中描述的新技术的特定方面。此外，尽管已在新技术的某些实施例的上下文中描述与那些实施例相关的优点，然而其它实施例也可展现此类优点且并非全部实施例需要展现此类优点以落在本技术的范围内。因此，本发明及相关技术可涵盖本文中未明确展示或描述的其它实施例。

Claims (27)

1.一种半导体裸片，其包括：
半导体衬底；
绝缘材料，其在所述半导体衬底的表面上方；
导电接点，其在所述半导体衬底的所述表面处且通过所述绝缘材料中的开口暴露；
互连结构，其包含电耦合到所述导电接点的导电材料，其中所述导电材料包含具有与所述导电接点垂直地对准的第一部分及横向延伸远离所述第一部分且在所述绝缘材料的至少一部分上方的第二部分的顶部表面，其中所述导电材料的所述顶部表面是润湿表面；
焊料材料，其至少部分安置于所述导电材料的所述顶部表面的所述第二部分上；及
至少部分在所述导电材料的所述顶部表面的所述第一部分上方的围阻层，其中所述围阻层包括防润湿材料以提供不可润湿表面。
2.根据权利要求1所述的半导体裸片，其中所述围阻层在所述导电材料的所述顶部表面的所述第一部分的全部上方。
3.根据权利要求1所述的半导体裸片，其中所述围阻层经配置以预防所述焊料材料从所述导电材料的所述顶部表面的所述第二部分芯吸到所述第一部分。
4.根据权利要求1所述的半导体裸片，其中所述围阻层是氧化物、氮化物或聚酰亚胺中的至少一者。
5.根据权利要求4所述的半导体裸片，其中所述围阻层包括氧化镍。
6.根据权利要求1所述的半导体裸片，其中所述互连结构进一步包含延伸在所述顶部表面与所述半导体衬底及所述接点之间的侧壁表面，且其中所述围阻层至少部分在所述侧壁表面上方。
7.根据权利要求1所述的半导体裸片，其中所述导电材料包括电耦合到所述导电接点的第一导电材料及安置于所述第一导电材料上方的第二导电材料。
8.根据权利要求7所述的半导体裸片，其中所述第一导电材料包括铜，其中所述第二导电材料包括镍，且其中所述绝缘材料包括钝化材料。
9.根据权利要求1所述的半导体裸片，其中所述导电接点是至少部分延伸穿过所述半导体衬底的接合垫或互连结构的一部分中的至少一者。
10.根据权利要求1所述的半导体裸片，其中所述焊料材料的部分未与所述导电接点垂直地对准。
11.根据权利要求1所述的半导体裸片，其中少于约50％的所述焊料材料与所述导电接点垂直地对准。
12.根据权利要求1所述的半导体裸片，其中少于约25％的所述焊料材料与所述导电接点垂直地对准。
13.一种半导体裸片，其包括：
半导体衬底；
第一接点，其暴露于所述半导体衬底的表面处；
第二接点，其暴露于所述半导体衬底的所述表面处；
第一互连结构，其电耦合到所述第一接点，其中所述第一互连结构包含具有所述
第一接点上方的第一部分及横向偏离所述第一接点的第二部分的顶部表面，其中所述第一互连结构的所述顶部表面是润湿表面；
至少在所述第一互连结构的所述第一部分上方的第一围阻层，其中所述第一围阻层包括防润湿材料以提供第一不可润湿表面；
第一焊料材料，其安置于所述第一互连结构的所述顶部表面的所述第二部分上；
第二互连结构，其电耦合到所述第二接点，其中所述第二互连结构包含具有所述
第二接点上方的第三部分及横向偏离所述第二接点的第四部分的顶部表面，其中所述第二互连结构的所述顶部表面是润湿表面；
至少在所述第二互连结构的所述第三部分上方的第二围阻层，其中所述第二围阻层包括防润湿材料以提供第二不可润湿表面；及
第二焊料材料，其安置于所述第二互连结构的所述顶部表面的所述第四部分上。
14.根据权利要求13所述的半导体裸片，其中所述第二接点与所述第一接点隔开第一距离，且其中所述第二焊料材料与所述第一焊料材料隔开大于所述第一距离的第二距离。
15.根据权利要求14所述的半导体裸片，其中所述第二距离是所述第一距离的至少两倍。
16.根据权利要求13所述的半导体裸片，其中所述第一互连结构的所述顶部表面在第一方向上从所述第一部分横向延伸到所述第二部分，其中所述第二互连结构的所述顶部表面在第二方向上从所述第三部分横向延伸到所述第四部分，且其中所述第一方向不同于所述第二方向。
17.根据权利要求16所述的半导体裸片，其中所述第一方向与所述第二方向大体上相反。
18.一种用于预防焊料桥接的方法，其包括：
通过将导电材料镀覆到半导体裸片的表面上且至少部分在所述半导体裸片的导电接点上方而在所述半导体裸片上建构互连结构使得所述互连结构电耦合到所述导电接点，并且所述互连结构的顶部表面的至少一部分与所述导电接点垂直地对准，其中所述互连结构的所述顶部表面是润湿表面；
在所述互连结构的所述顶部表面的至少一第一部分上形成围阻层，其中所述围阻层包括防润湿材料以提供不可润湿表面；及
在所述互连结构的所述顶部表面的第二部分上安置焊料材料，其中所述互连结构的所述顶部表面的所述第二部分至少部分横向偏离所述半导体裸片的所述导电接点。
19.根据权利要求18所述的方法，其中建构所述互连结构包含(a)将第一导电材料镀覆到所述导电接点上且将绝缘材料镀覆于所述半导体裸片的所述表面处，及(b)将第二导电材料镀覆到所述第一导电材料上。
20.根据权利要求18所述的方法，其进一步包括在所述互连结构上形成所述围阻层之前于所述互连结构上安置所述焊料材料。
21.根据权利要求20所述的方法，其中形成所述围阻层包含在所述焊料材料的表面上方形成所述围阻层。
22.根据权利要求21所述的方法，其进一步包括使所述焊料材料回流，其中使所述焊料材料回流至少部分从所述焊料材料的所述表面移除所述围阻层。
23.根据权利要求18所述的方法，其进一步包括在将所述焊料材料安置于所述互连结构上之前在所述互连结构上形成所述围阻层。
24.根据权利要求23所述的方法，其中所述围阻层包括围阻材料，且其中形成所述围阻层包含：
在所述互连结构的所述顶部表面的全部上方形成所述围阻材料的层；及
移除所述互连结构的所述顶部表面的所述第二部分上的所述围阻材料的一部分。
25.根据权利要求18所述的方法，其中形成所述围阻层包含至少部分将所述互连结构暴露到等离子体。
26.根据权利要求25所述的方法，其中所述等离子体是氧等离子体，且其中所述围阻层包括氧化物。
27.根据权利要求18所述的方法，其中形成所述围阻层包含在所述互连结构的侧壁表面上方形成所述围阻层。
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