CN107342236A - 半导体封装件的制造方法 - Google Patents
半导体封装件的制造方法 Download PDFInfo
- Publication number
- CN107342236A CN107342236A CN201710239394.XA CN201710239394A CN107342236A CN 107342236 A CN107342236 A CN 107342236A CN 201710239394 A CN201710239394 A CN 201710239394A CN 107342236 A CN107342236 A CN 107342236A
- Authority
- CN
- China
- Prior art keywords
- semiconductor package
- manufacture method
- package part
- insulating barrier
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 210
- 239000004065 semiconductor Substances 0.000 title claims abstract description 180
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 112
- 229920005989 resin Polymers 0.000 claims abstract description 111
- 239000011347 resin Substances 0.000 claims abstract description 111
- 230000004888 barrier function Effects 0.000 claims abstract description 89
- 239000000463 material Substances 0.000 claims abstract description 37
- 238000009832 plasma treatment Methods 0.000 claims abstract description 25
- 239000000126 substance Substances 0.000 claims abstract description 25
- 238000010129 solution processing Methods 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 238000012545 processing Methods 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 29
- 239000000945 filler Substances 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 9
- 230000008961 swelling Effects 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 229910010272 inorganic material Inorganic materials 0.000 claims description 2
- 239000011147 inorganic material Substances 0.000 claims description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims 6
- 229910052748 manganese Inorganic materials 0.000 claims 6
- 239000011572 manganese Substances 0.000 claims 6
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 claims 3
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims 3
- 229910052700 potassium Inorganic materials 0.000 claims 3
- 239000011591 potassium Substances 0.000 claims 3
- 229910052708 sodium Inorganic materials 0.000 claims 3
- 239000011734 sodium Substances 0.000 claims 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 76
- 230000008569 process Effects 0.000 description 69
- 239000000853 adhesive Substances 0.000 description 47
- 230000001070 adhesive effect Effects 0.000 description 47
- 229910000679 solder Inorganic materials 0.000 description 26
- 238000000576 coating method Methods 0.000 description 23
- 239000000243 solution Substances 0.000 description 23
- 239000011248 coating agent Substances 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 239000010949 copper Substances 0.000 description 15
- 238000007788 roughening Methods 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000007772 electroless plating Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 7
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 238000001878 scanning electron micrograph Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910001128 Sn alloy Inorganic materials 0.000 description 3
- 238000002679 ablation Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000005868 electrolysis reaction Methods 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- 239000011135 tin Substances 0.000 description 3
- JYLNVJYYQQXNEK-UHFFFAOYSA-N 3-amino-2-(4-chlorophenyl)-1-propanesulfonic acid Chemical compound OS(=O)(=O)CC(CN)C1=CC=C(Cl)C=C1 JYLNVJYYQQXNEK-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 208000004350 Strabismus Diseases 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- MTHSVFCYNBDYFN-UHFFFAOYSA-N anhydrous diethylene glycol Natural products OCCOCCO MTHSVFCYNBDYFN-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000004821 distillation Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001802 infusion Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000012286 potassium permanganate Substances 0.000 description 2
- -1 printing element Substances 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000010944 silver (metal) Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- WSQZNZLOZXSBHA-UHFFFAOYSA-N 3,8-dioxabicyclo[8.2.2]tetradeca-1(12),10,13-triene-2,9-dione Chemical compound O=C1OCCCCOC(=O)C2=CC=C1C=C2 WSQZNZLOZXSBHA-UHFFFAOYSA-N 0.000 description 1
- ZNBNBTIDJSKEAM-UHFFFAOYSA-N 4-[7-hydroxy-2-[5-[5-[6-hydroxy-6-(hydroxymethyl)-3,5-dimethyloxan-2-yl]-3-methyloxolan-2-yl]-5-methyloxolan-2-yl]-2,8-dimethyl-1,10-dioxaspiro[4.5]decan-9-yl]-2-methyl-3-propanoyloxypentanoic acid Chemical compound C1C(O)C(C)C(C(C)C(OC(=O)CC)C(C)C(O)=O)OC11OC(C)(C2OC(C)(CC2)C2C(CC(O2)C2C(CC(C)C(O)(CO)O2)C)C)CC1 ZNBNBTIDJSKEAM-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000004425 Makrolon Chemical class 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004696 Poly ether ether ketone Substances 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 229920002873 Polyethylenimine Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004721 Polyphenylene oxide Chemical class 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 125000002252 acyl group Chemical group 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004643 cyanate ester Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229940028356 diethylene glycol monobutyl ether Drugs 0.000 description 1
- BNBLBRISEAQIHU-UHFFFAOYSA-N disodium dioxido(dioxo)manganese Chemical compound [Na+].[Na+].[O-][Mn]([O-])(=O)=O BNBLBRISEAQIHU-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000635 electron micrograph Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 229910000378 hydroxylammonium sulfate Inorganic materials 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 150000002466 imines Chemical group 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 150000002825 nitriles Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- JCGNDDUYTRNOFT-UHFFFAOYSA-N oxolane-2,4-dione Chemical compound O=C1COC(=O)C1 JCGNDDUYTRNOFT-UHFFFAOYSA-N 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920001230 polyarylate Polymers 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 229920000515 polycarbonate Chemical class 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920002530 polyetherether ketone Polymers 0.000 description 1
- 229920001601 polyetherimide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000098 polyolefin Polymers 0.000 description 1
- 229920006324 polyoxymethylene Polymers 0.000 description 1
- 229920006380 polyphenylene oxide Chemical class 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229910052623 talc Inorganic materials 0.000 description 1
- 239000000454 talc Substances 0.000 description 1
- 235000012222 talc Nutrition 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
- H01L24/64—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0363—Manufacturing methods by patterning a pre-deposited material using a laser or a focused ion beam [FIB]
- H01L2224/03632—Ablation by means of a laser or focused ion beam [FIB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8201—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Ceramic Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
本发明提供一种用于获得半导体装置与布线之间的良好的接触的半导体封装件的制造方法。所述半导体封装件的制造方法包括如下步骤:在基材上配置上部面设有外部端子的半导体装置;形成覆盖半导体装置的树脂绝缘层;在树脂绝缘层形成用于露出外部端子的开口部;在形成开口部之后,对开口部的底部进行等离子处理;在等离子处理之后,对开口部的底部进行化学溶液处理;以及形成与在开口部中被露出的外部端子相连接的导体。
Description
技术领域
本发明涉及半导体封装件的制造方法。尤其,本发明涉及在基材上的半导体装置的封装技术。
背景技术
以往,在移动电话或智能电话等的电子设备中采用在支承基板上搭载有集成电路(integrated circuit,IC)芯片等半导体装置的半导体封装件结构(例如日本特开2010-278334号公报)。在这种半导体封装件中,通常采用如下结构:在支承基材上通过粘接层接合IC芯片或存储器等的半导体装置,并通过利用密封体(密封用树脂材料)覆盖该半导体装置,来保护半导体器件。
作为用于半导体装置的支承基材,采用印刷基材、陶瓷基材等各种基材。尤其,近年来,对于使用金属基材的半导体封装件的开发研究不断推进。在金属基材上搭载有半导体装置并通过再布线来扇出的半导体封装件具有电磁屏蔽性能、热性能优良的优点,作为高可靠性的半导体封装件而备受瞩目。这种半导体封装件还具有封装设计的自由度高的优点。
在支承基材上搭载半导体装置的结构的情况下,通过在大型支承基材上搭载多个半导体装置,能够利用同一工序来制造多个半导体封装件。在这种情况下,形成在支承基材上的多个半导体封装件,在制造过程结束之后被单片化,从而完成各个半导体封装件。像这种在支承基材上搭载有半导体装置的半导体封装件的结构具有生产率高的优点。
发明内容
如上所述,在考虑到使用大型金属基材为支承基材的大量生产方法的情况下,需要满足如下条件:向该金属基材配置半导体装置时的高对准精度、半导体装置与布线之间的良好的接触、或成品率高的半导体封装件的单片化等。
本发明是鉴于这些技术问题而提出的,其目的在于提供一种用于获得半导体装置与布线之间的良好的接触的半导体封装件的制造方法。
本发明的一个实施方式的半导体封装件的制造方法,包括如下步骤:在基材上配置上部面设有外部端子的半导体装置;形成覆盖半导体装置的树脂绝缘层;在树脂绝缘层形成用于露出外部端子的开口部;在形成开口部之后,对所述开口部的底部进行等离子处理;在等离子处理之后,对所述开口部的底部进行化学溶液处理;以及形成与在开口部中被露出的外部端子相连接的导体。
根据本发明的半导体封装件的制造方法,能够提供用于获得半导体装置与布线之间的良好接触的半导体封装件的制造方法。
附图说明
图1为本发明的一个实施方式的半导体封装件的截面示意图。
图2为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材形成对准标记的工序的图。
图3为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材形成粘接层的工序的图。
图4为示出在本发明的一个实施方式的半导体封装件的制造方法中,对支承基材的背面和侧面进行粗化的工序的图。
图5为示出在本发明的一个实施方式的半导体封装件的制造方法中,去除粘接层的一部分的工序的图。
图6为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材配置半导体装置的工序的图。
图7为示出在本发明的一个实施方式的半导体封装件的制造方法中,形成树脂绝缘层的工序的图。
图8为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层上形成导电层的工序的图。
图9为示出在本发明的一个实施方式的半导体封装件的制造方法中,对导电层的表面进行粗化的工序的图。
图10为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层形成开口部的工序的图。
图11为示出在本发明的一个实施方式的半导体封装件的制造方法中,去除导电层的表面的进行了粗化的区域,并去除开口底部的残渣的工序的图。
图12为示出在本发明的一个实施方式的半导体封装件的制造方法中,利用无电解镀敷法形成导电层的工序的图。
图13为示出在本发明的一个实施方式的半导体封装件的制造方法中,形成感光性光刻胶的工序的图。
图14为示出在本发明的一个实施方式的半导体封装件的制造方法中,利用光刻去除感光性光刻胶的一部分的工序的图。
图15为示出在本发明的一个实施方式的半导体封装件的制造方法中,利用电解镀敷法形成导电层的工序的图。
图16为示出在本发明的一个实施方式的半导体封装件的制造方法中,去除感光性光刻胶的工序的图。
图17为示出在本发明的一个实施方式的半导体封装件的制造方法中,通过去除导电层的一部分来形成布线的工序的图。
图18为示出在本发明的一个实施方式的半导体封装件的制造方法中,形成覆盖布线的树脂绝缘层的工序的图。
图19为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层形成用于露出布线的开口部的工序的图。
图20为示出在本发明的一个实施方式的半导体封装件的制造方法中,在与被露出的布线相对应的位置配置焊料球的工序的图。
图21为示出在本发明的一个实施方式的半导体封装件的制造方法中,将焊料球回流的工序的图。
图22为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层形成达到支承基材的槽的工序的图。
图23为示出在本发明的一个实施方式的半导体封装件的制造方法中,通过切割支承基材来对半导体封装件进行单片化的工序的图。
图24为本发明的一个实施方式的半导体封装件的截面示意图。
图25为示出在本发明的一个实施方式的半导体封装件的制造方法中,准备支承基材的工序的图。
图26为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材形成粘接层的工序的图。
图27为示出在本发明的一个实施方式的半导体封装件的制造方法中,对支承基材的背面和侧面进行粗化的工序的图。
图28为示出在本发明的一个实施方式的半导体封装件的制造方法中,在粘接层形成对准标记的工序的图。
图29为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材上配置半导体装置的工序的图。
图30为示出在本发明的一个实施例中的树脂绝缘层的开口部中进行残渣去除处理之前和之后的电子显微图像的图。
(附图标记的说明)
10、20:半导体封装件;100:支承基材;102、114:对准标记;
104、146:粗化区域;110:粘接层;112:开口部;120:半导体装置;
122:外部端子;130:第一树脂绝缘层;132:开口部;140:布线;
142:第一导电层;144:第二导电层;150:第二树脂绝缘层;152:开口部;
160:焊料球;200:镀层;210:光刻胶;220:抗蚀图案;
230:厚膜区域;240:薄膜区域;250:切口
具体实施方式
以下,参照附图,对本发明的一个实施方式的半导体封装件的结构及其制造方法进行详细说明。以下所示的实施方式只是本发明的实施方式的一个示例,不应局限于这些实施方式来解释本发明。在本实施方式所参照的附图中,存在对同一部分或具有相同功能的部分赋予同一附图标记或类似的附图标记而省略对其的反复说明的情况。为了便于说明,存在附图的尺寸比率与实际的比率不同或结构的一部分从附图中省略的情况。为了便于说明,利用上方或下方的语句来进行说明,但可以配置成例如第一部件与第二部件之间的上下关系与图示相反的结构。以下的说明中基板的第一面和第二面不指基板的特定面,而是用于确定基板的表面方向或背面方向,换言之是用于确定对于基板的上下方向的名称。
<实施方式1>
参照图1,对本发明的实施方式1的半导体封装件的概述进行详细说明。图1为本发明的一个实施方式的半导体封装件的截面示意图。
(半导体封装件10的结构)
如图1所示,半导体封装件10具有支承基材100、粘接层110、半导体装置120、第一树脂绝缘层130、布线140、第二树脂绝缘层150及焊料球160。
支承基材100设置有支承基材100的一部分呈凹陷的形状的对准标记102。粘接层110配置于支承基材100的表面。粘接层110以露出对准标记102的方式而开口。粘接层110的开口比对准标记102的区域更宽。对准标记102及其周边的支承基材100的表面通过此开口来被露出。半导体装置120配置在粘接层110上。半导体装置120的上部设置有与半导体装置120所包括的电子电路相连接的外部端子122。在图1中示出了粘接层110为单层的结构,但不限于此结构。例如,粘接层110可以为多层。
第一树脂绝缘层130以覆盖半导体装置120的方式配置在支承基材100上。在第一树脂绝缘层130设置有开口部132。开口部132达到外部端子122。换言之,开口部132设置为露出外部端子122。
布线140具有第一导电层142和第二导电层144。第一导电层142配置于第一树脂绝缘层130的上部面。第二导电层144配置在第一导电层142上和开口部132的内部,并与外部端子122相连接。在图1中,例示了如下的结构,即,第一导电层142仅配置于第一树脂绝缘层130的上部面,而完全未配置在开口部132的内部,但不限于此结构。例如第一导电层142的一部分可以配置于开口部132的内部。第一导电层142和第二导电层144的各个可以为图1所示的单层,但第一导电层142和第二导电层的一者或两者也可以为多层。
第二树脂绝缘层150以覆盖布线140的方式配置在第一树脂绝缘层130上。第二树脂绝缘层150设置有开口部152。开口部152达到布线140。换言之,开口部152配置为露出布线140。
焊料球160配置于开口部152的内部和第二树脂绝缘层150的上部面,并与布线140相连接。焊料球160的上部面从第二树脂绝缘层150的上部面向上方突出。焊料球160的突出部具有向上凸起的弯曲形状。焊料球160的弯曲形状在剖视图中可以为圆弧,也可以为抛物线。
(半导体封装件10的各个部件的材料)
对包括在图1所示的半导体封装件10中的各个部件(各个层)的材料进行详细说明。
作为支承基材100,可以使用金属基材。作为金属基材,可以使用不锈钢(SUS)基材、铝(Al)基材、钛(Ti)基材及铜(Cu)等的金属材料。作为支承基材100,除了金属基材之外还可以使用硅基板、炭化硅基板及化合物半导体基板等的半导体基材。由于SUS基材的热膨胀系数低且价格低,因此优选地,作为支承基材100使用SUS基材。
作为粘接层110,可以使用包含环氧类树脂或丙烯酸类树脂的粘接剂。
作为半导体装置120,可以使用中央处理单元(Central Processing Unit,CPU)、存储器、微机电系统(Micro Electro Mechanical Systems,MEMS)及功率半导体器件(功率器件,power device)等。
作为第一树脂绝缘层130和第二树脂绝缘层150,可以使用聚酰亚胺、环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚酰胺、酚醛树脂、硅酮树脂、氟树脂、液晶聚合物、聚酰胺酰亚胺、聚苯并恶唑、氰酸酯树脂、芳族聚酰胺、聚烯烃、聚酯、BT树脂、FR-4、FR-5、聚缩醛、聚对苯二甲酸丁二酯、间规聚苯乙烯、聚苯硫醚、聚醚醚酮、聚醚腈、聚碳酸酯、聚苯醚类聚砜、聚醚砜、聚芳酯及聚醚酰亚胺等。环氧类树脂具有优异的电气特性和加工特性,因此优选地,作为第一树脂绝缘层130和第二树脂绝缘层150使用环氧类树脂。
在本实施方式中所使用的第一树脂绝缘层130包括填料。作为填料,可以使用玻璃、滑石、云母、二氧化硅及氧化铝等的无机填料。作为填料,也可以使用氟树脂填料等的有机填料。但是,第一树脂绝缘层130并不限定为必须为包括填料的树脂。在本实施方式中,第二树脂绝缘层150包括填料,但也可以在第二树脂绝缘层150不包括有填料。
作为第一导电层142和第二导电层144,可以从铜(Cu)、金(Au)、银(Ag)、铂(Pt)、铑(Rh)、锡(Sn)、铝(Al)、镍(Ni)、钯(Pd)及铬(Cr)等的金属或使用这些的合金等中选择。第一导电层142和第二导电层144可以使用相同的材料,也可以使用不同的材料。
作为焊料球160,可以使用由例如在Sn中添加了少量的Ag、Cu、Ni、铋(Bi)或锌(Zn)的锡合金而形成的球状的物体。除了焊料球以外,也可以使用通常的导电颗粒。例如,作为导电颗粒,可以使用在颗粒状的树脂的周边形成有导电膜的物体。除了焊料球以外,也可以使用焊膏。作为焊膏,可以使用Sn、Ag、Cu、Ni、Bi、磷(P)、锗(Ge)、铟(In)、锑(Sb)、钴(Co)及铅(Pb)。
(半导体封装件10的制造方法)
利用图2至图23,对本发明的实施方式1的半导体封装件10的制造方法进行说明。在图2至图23中,对于与由图1所示的要素相同的要素赋予相同的附图标记。在以下说明中,对半导体封装件的制造方法进行说明,其中,作为支承基材100使用SUS基材,作为第一树脂绝缘层130使用环氧类树脂,作为第一导电层142以及第二导电层144使用Cu,作为焊料球160使用上述Sn合金,来制造半导体封装件。
图2为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材上形成对准标记的工序的图。利用光刻及蚀刻来形成对准标记102。对准标记102的位置及平面形状可以根据目的适当决定。对准标记102设置为具有当利用光学显微镜等从上部面侧观察支承基材100时,能够视觉辨识的程度的高度差即可。
图3为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材形成粘接层的工序的图。在形成有对准标记102的支承基材100的上部面形成粘接层110。作为粘接层110粘贴片状的粘接层。可以利用涂敷法涂覆处于溶解于溶剂的状态的粘接层材料来作为粘接层110。在图3中,对准标记102的凹部为空洞状态,但形成有对准标记102的区域的粘接层110在后续工序中被去除,因此在该工序中,粘接层110可以掩埋对准标记102的凹部。
图4为示出在本发明的一个实施方式的半导体封装件的制造方法中,对支承基材的背面及侧面进行粗化的工序的图。为了抑制在后续工序中利用无电解镀敷法形成的镀层的剥离现象,而对支承基材100的背面及侧面进行粗化(或粗面化处理)处理。支承基材100的粗化可以通过使用包含Cu的化学溶液(蚀刻液)进行。在图4中,用虚线来表示粗化区域104。
对支承基材100的粗化进行更详细的说明。在支承基材100使用SUS基材时,SUS基材的表面被处理为非导体状态。包含在所述蚀刻液的Cu离子被SUS基材中的铁(Fe)、铬(Cr)及Ni中的至少一个置换。通过Cu离子与Fe、Cr、Ni的至少一个之间的置换,来进行SUS的蚀刻。但是,由于局部进行SUS的蚀刻,SUS被不均匀地蚀刻。因此,蚀刻之后的SUS表面的凹凸会变大。即,由于在图4所示的状态下浸渍于蚀刻液中,可利用同一处理来对SUS基材的背面及侧面进行粗化。
其中,例示出粘贴粘接层110之后对SUS基材进行粗化的制造方法,但不限于此制造方法。例如,可以在粘贴粘接层110之前,或在形成对准标记102之前进行粗化。
图5为示出在本发明的一个实施方式的半导体封装件的制造方法中,去除粘接层的一部分的工序的图。为了更加精良地读取对准标记102,去除对准标记102的上方的粘接层110来形成开口部112。粘接层110的去除可利用基于激光照射的升华或烧蚀(ablation)来进行。开口部112可以利用光刻及蚀刻来形成。开口部112为了可靠地露出对准标记102,而形成在比对准标记102宽的区域。即,开口部112露出支承基材100的上部面(形成有对准标记102的面侧)。换言之,开口部112形成为在俯视图中,开口部112的外缘包围对准标记102的外缘。
图6为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材上配置半导体装置的工序的图。如上所述基于露出的对准标记102来进行位置对准,并通过粘接层110将在上部面具有外部端子122的半导体装置120配置于支承基材100。对准标记102的读取可以利用例如光学显微镜、CCD摄像机及电子显微镜等的方法来进行。通过这些方法,能够以高定位精度来实现半导体装置120的安装。
图7为示出在本发明的一个实施方式的半导体封装件的制造方法中,形成树脂绝缘层的工序的图。第一树脂绝缘层130通过粘贴绝缘性的片状膜来形成。具体而言,在将该片状膜粘贴于安装有半导体装置120的支承基材100之后,利用加热处理使片状膜熔化。通过加压处理将熔化的片状膜掩埋于对准标记102的凹部。通过该加热处理以及加压处理从所述片状膜中获得图7所示的第一树脂绝缘层130。第一树脂绝缘层130的膜厚设定为第一树脂绝缘层130覆盖半导体装置120的程度。即,第一树脂绝缘层130的膜厚大于半导体装置120的厚度(高度)。第一树脂绝缘层130因缓和(平坦化)由半导体装置120、粘接层110等形成的高度差,而被称作平坦化膜。
第一树脂绝缘层130防止半导体装置120以及外部端子122与布线140之间的导通。即,在半导体装置120以及外部端子122与布线140之间设置有间隙。若第一树脂绝缘层130配置于半导体装置120和外部端子122的至少上部面及侧面,则第一树脂绝缘层130的膜厚可以小于半导体装置120的厚度。在图7的说明中,例示出通过片状膜的粘贴来形成第一树脂绝缘层130的制造方法,但不限于此方法。例如可以通过旋涂法、浸渍法、喷墨法及蒸镀法等各种方法来形成第一树脂绝缘层130。
图8为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层上形成导电层的工序的图。在第一树脂绝缘层130的上部面粘贴具有导电性的片状膜。该导电性膜为第一导电层142的一部分。在此,例示了通过膜的粘贴来形成第一导电层142的制造方法,但不限于此方法。例如第一导电层142可以利用镀敷法或物理气相沉积(Physical Vapor Deposition,PVD)法来形成。作为物理气相沉积法,可以使用溅射法、真空蒸镀法、电子束蒸镀法及分子束外延法等。可以通过涂敷溶解有具有导电性的树脂材料的溶剂,来形成第一导电层142。
图9为示出在本发明的一个实施方式的半导体封装件的制造方法中,对导电层的表面进行粗化的工序的图。如图9所示,对形成在第一树脂绝缘层130上的第一导电层142的表面进行粗化。对于第一导电层142表面的粗化,可以通过使用三氯化铁溶液的蚀刻来进行。在图9中,用虚线来表示粗化区域146。
图10为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层形成开口部的工序的图。如图10所示,在与外部端子122相对应的位置,用激光照射第一导电层142表面的粗化区域146,来形成露出外部端子122的开口部132。在开口部132的形成中,可以一并处理第一导电层142和第一树脂绝缘层130。作为用于形成开口部132的激光,可以使用CO2激光。关于CO2激光,可以根据开口部132的大小来调整光斑直径以及能量大小,并进行多次脉冲照射。可通过在第一导电层142的表面形成粗化区域146,来使第一导电层142高效地吸收所照射的激光束的能量。激光束被照射到外部端子122的内侧。即,以不脱落外部端子122的图案的方式来照射激光束。当需要加工半导体装置120的一部分时,也可以以有意使激光束的一部分露出于外部端子122的外侧的方式照射。
在图10中,例示出被开口的第一导电层142的侧壁与第一树脂绝缘层130的侧壁相连接的结构,但是不限于此结构。例如,在被激光照射而开口的情况下,存在与第一导电层142相比,第一树脂绝缘层130的一侧更向支承基材100的平面方向(开口直径变宽的方向)大幅后退的情况。即,可以是第一导电层142的端部比第一树脂绝缘层130的端部更向开口部132的内侧方向突出的结构。换言之,可以是第一导电层142突出的檐形状。或者换言之,当形成开口部132时,第一导电层142的一部分的下部面可以露出于开口部132的内部。此时,突出的第一导电层142可以呈在开口部132的内部中向外部端子122的方向弯曲的形状。
图11为示出在本发明的一个实施方式的半导体封装件的制造方法中,去除导电层的表面的被粗化的区域,并去除开口底部的残渣的工序的图。首先,在形成开口部132之后,去除第一导电层142表面的粗化区域146。可以通过酸处理来去除粗化区域146。去除粗化区域146之后,接着去除开口部132的底部的残渣(胶渣,smear)。通过两个步骤的工序来去除残渣(除胶渣)。
对去除开口部132的底部的残渣的方法进行详细说明。首先,对开口部132的底部进行等离子处理。作为等离子处理,可以利用包含氟(CF4)气及氧(O2)气的等离子处理。通过等离子处理,主要去除在形成开口部132时未被去除的第一树脂绝缘层130。此时,可以去除在形成开口部132时产生的第一树脂绝缘层130的变质层。例如,在利用激光照射来形成开口部132的情况下,存在因激光的能量而变质的第一树脂绝缘层130残留在开口部132的底部的情况。可通过如上所述地进行等离子处理,来有效地去除上述变质层。
在所述等离子处理之后,接着进行化学溶液处理。作为化学溶液处理,可以使用高锰酸钠或高锰酸钾。利用化学溶液处理,能够去除未被所述等离子处理去除的残渣。例如,能够去除包含在第一树脂绝缘层130且在所述等离子处理中未被去除的填料。高锰酸钠或高锰酸钾是具有用于蚀刻残渣的作用的蚀刻液。可以在利用所述蚀刻液来进行处理之前,使用使第一树脂绝缘层130溶胀(swelling)的溶胀液。可以在利用所述蚀刻液进行处理之后,使用中和蚀刻液的中和液。
通过使用溶胀液而扩大树脂环,因此液体的润湿性提高。由此,能够抑制出现不被蚀刻的区域的情况。通过使用中和液,能够高效地去除蚀刻液,因此能够抑制不期望的蚀刻处理的进行。例如,在蚀刻液使用碱性溶液的情况下,由于利用水洗处理很难去除碱性溶液,因此存在不期望的蚀刻处理不断进行的情况。在这种情况下,在蚀刻处理之后,若利用中和液,则能抑制不期望的蚀刻处理的进行。
作为溶胀液,可以使用二甘醇单丁基醚、乙二醇等的有机溶剂。作为中和液,可以使用羟胺硫酸盐等的硫酸类溶液。
例如,在第一树脂绝缘层130使用无机材料的填料的情况下,存在如下情况,即,填料未被等离子处理去除,而成为残渣。即使在这种情况下,也可通过在等离子处理之后进行化学溶液处理,来去除由填料引起的残渣。
图12为示出在本发明的一个实施方式的半导体封装件的制造方法中,利用无电解镀敷法形成导电层的工序的图。利用无电解镀敷法,形成与在所述除胶渣工序之后露出的外部端子122相连接的镀层200(导体)。无电解镀敷法为使钯(Pd)胶体吸附于树脂之后浸渍于包含铜的化学溶液中,并通过钯与铜的置换,来析出铜的方法。通过在去除粗化区域146之后利用无电解镀敷法形成镀层200,能够提高镀层200对于第一导电层142的紧贴性。
图13为示出在本发明的一个实施方式的半导体封装件的制造方法中,形成感光性光刻胶(photoresist)的工序的图。如图13所示,在镀层200上形成感光性的光刻胶210。光刻胶通过旋涂法等的涂敷法来形成。在形成光刻胶之前,可以进行提高镀层200与光刻胶210之间的紧贴性的处理(HMDS处理等的疏水化表面处理)。光刻胶210可以使用利用显影液难以蚀刻被感光的区域的负型,相反,也可以使用利用显影液来蚀刻被感光的区域的正型。
图14为示出本发明的一个实施方式的半导体封装件的制造方法中,利用光刻去除感光性光刻胶的一部分的工序的图。如图14所示,通过对涂敷的光刻胶210进行曝光及显影,来去除形成图1所示的布线140的区域的光刻胶210,从而形成抗蚀图案(resistpattern)220。此外,在进行形成抗蚀图案220的曝光时,利用形成于支承基材100的对准标记102来进行位置对准。
图15为示出在本发明的一个实施方式的半导体封装件的制造方法中,利用电解镀敷法来形成导电层的工序的图。在形成抗蚀图案220之后,对利用无电解镀敷法形成的镀层200通电,来进行电解镀敷法,从而使从抗蚀图案220露出的镀层200进一步成长并加厚,以形成第二导电层144。抗蚀图案220之下的第一导电层142及镀层200因对整体的蚀刻而被去除,因此被加厚的第二导电层144的膜也变薄。因此,考虑到所述膜的变薄量来调整需要加厚的第二导电层144的量。
图16为示出在本发明的一个实施方式的半导体封装件的制造方法中,去除感光性光刻胶的工序的图。如图16所示,在通过加厚镀层200来形成第二导电层144之后,利用有机溶剂来去除构成抗蚀图案220的光刻胶。在去除光刻胶时,可以代替有机溶剂来使用基于氧等离子的灰化(ashing)。可通过去除光刻胶,来获得形成有第二导电层144的厚膜区域230及仅形成有镀层200的薄膜区域240。此外,在厚膜区域230中,在镀层200上利用电解镀敷法形成有加厚的镀层,因此,严格地说,第二导电层144形成为双层,但在此处不区分两层来图示。
图17为示出在本发明的一个实施方式的半导体封装件的制造方法中,去除导电层的一部分来形成布线的工序的图。如图17所示,通过去除(蚀刻)被抗蚀图案220覆盖而未被加厚的区域的镀层200及第一导电层142,来将各个布线140电隔离。通过镀层200及第一导电层142的蚀刻,厚膜区域230的第二导电层144的表面也被蚀刻并薄膜化,因此优选地,在考虑到该薄膜化的影响下设定第二导电层144的膜厚。作为该工序的蚀刻,可以使用湿法刻蚀或干法蚀刻。在图17中,例示了形成一层的布线140的制造方法,但不限于此方法,可以使绝缘层及导电层层叠在布线140的上方,来形成层叠有多个布线层的多层布线。此时,在每次形成布线层时形成新的对准标记,从而用于形成上层的布线层时的位置对准。
图18为示出在本发明的一个实施方式的半导体封装件的制造方法中,形成覆盖布线的树脂绝缘层的工序的图。第二树脂绝缘层150与第一树脂绝缘层130相同,通过粘贴绝缘性的片状膜,并进行加热/加压处理来形成。第二树脂绝缘层150的膜厚被设定为第二树脂绝缘层150覆盖布线140。即,第二树脂绝缘层150的膜厚大于布线140的厚度。第二树脂绝缘层150因缓和(平坦化)由布线140等而形成的高度差,而被称作平坦化膜。
第二树脂绝缘层150防止布线140与焊料球160导通。即,在布线140与焊料球160之间设有间隙(gap)。若第二树脂绝缘层150配置于布线140的至少上部面及侧面,则第二树脂绝缘层150的膜厚可以比布线140的厚度薄。在图18的说明中,例示了通过粘贴片状膜来形成第二树脂绝缘层150的制造方法,但不限于此方法。例如可以利用旋涂法、浸渍法、喷墨法及蒸镀法等各种方法来形成第二树脂绝缘层150。
图19为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层形成露出布线的开口部的工序的图。如图19所示,在第二树脂绝缘层150形成露出布线140的开口部152。开口部152可以通过光刻及蚀刻来形成。在作为第二树脂绝缘层150使用感光性树脂的情况下,开口部152可以通过曝光及显影来形成。也可以对开口部152实施对第一树脂绝缘层130的开口部132实施的除胶渣处理。可通过基于以与形成布线140相同的工序形成的对准标记进行位置对准,来形成开口部152。
图20为示出在本发明的一个实施方式的半导体封装件的制造方法中,在与露出的布线相对应的位置配置焊料球的工序的图。如图20所示,针对开口部152配置焊料球160。在图20中,例示了在一个开口部152配置一个焊料球160的制造方法,但不限于此方法。例如,可以针对一个开口部152配置多个焊料球160。在图20中,例示了在将焊料球160配置于开口部152的步骤中,焊料球160与布线140相接触的制造方法,但不限于此方法。例如,在图20所示的步骤中,焊料球160也可以不与布线140相接触。可通过基于以与形成布线140相同的工序形成的对准标记进行位置对准,来配置焊料球160。
图21为示出在本发明的一个实施方式的半导体封装件的制造方法中,回流(reflow)焊料球的工序的图。通过在图20所示的状态下进行热处理,来使焊料球160回流。回流是指使固体的对象物的至少一部分变为液状,来赋予对象物流动性,由此使对象物流入凹部的内部。可通过回流焊料球160,在开口部152的内部中露出的布线140的上部面的整个区域中使焊料球160与布线140相接触。
图22为示出在本发明的一个实施方式的半导体封装件的制造方法中,在树脂绝缘层形成达到支承基材的槽的工序的图。在此,利用划片刀(例如金刚石制圆形旋转刀刃)在粘接层110、第一树脂绝缘层130及第二树脂绝缘层150划出切口250。切口250是通过使划片刀高速旋转,并用纯水进行冷却/切屑的冲洗的同时进行切断而形成的。在图22中,切口250形成于粘接层110、第一树脂绝缘层130及第二树脂绝缘层150。但,也可以划片到达支承基材100来形成切口250。即,可通过划片来在支承基材100的上部面附近形成凹部。相反,也可以以残留粘接层110的一部分、或粘接层110及第一树脂绝缘层130的一部分的方式进行划片。
图23为示出在本发明的一个实施方式的半导体封装件的制造方法中,通过切断支承基材来对半导体封装件进行单片化的工序的图。如图23所示,通过从支承基材100的背面侧(与配置有半导体装置120的一侧的相反一侧)开始激光照射,来对半导体封装件进行单片化。作为向支承基材100照射的激光,可以使用CO2激光。可通过基于支承基材100的对准标记102进行位置对准,来进行激光照射。激光被照射在比俯视图中的切口250小的区域。
在此,示出了从支承基材100的背面侧进行激光照射的制造方法,但不限于此方法。例如,可以从支承基材100的表面侧经由切口250,来从支承基材100的表面侧进行激光照射。在上述说明中,示出了向俯视图中比形成有切口250的区域小的区域照射激光的制造方法,但不限于此方法。例如,可以向俯视图中与形成有切口250的区域相同的区域照射激光,也可以在更宽的区域照射激光。
在此,在支承基材100使用金属基材的情况下,若将粘接层110、第一树脂绝缘层130、第二树脂绝缘层150及支承基材100一并加工,则划片刀的磨耗变大,进而划片刀的使用寿命变短。另外,若利用划片刀对金属基材进行机械加工,则在加工端部中的角形状上会产生尖锐的“毛刺”,进而在装卸时存在作业人受伤的危险。但是,通过对支承基材100进行激光加工,能够抑制划片刀的磨耗,进而可使支承基材100的加工端部的形状光滑。因此,尤其在作为支承基材100使用金属基材的情况下,优选地,如上所述,利用划片刀来加工支承基材100上的结构物,利用激光加工支承基材100。
如上所示,根据实施方式1的半导体封装件的制造方法,在去除在树脂绝缘层130的开口部132的底部存在的残渣时,通过进行等离子处理及化学溶液处理这两个步骤的处理,能够高效地去除开口部132的底部(外部端子122的上部)的残渣。其结果,减少了布线140与外部端子122之间的接触阻力,提高了两者之间的紧贴性。因此,根据实施方式1的半导体封装件的制造方法,能够提供用于获得半导体装置与布线之间的良好接触的半导体封装件的制造方法。
<实施方式2>
参照图24,对本发明的实施方式2的半导体封装件的概要进行详细说明。图24为本发明的一个实施方式的半导体封装件的截面示意图。
(半导体封装件20的结构)
实施方式2的半导体封装件20类似于实施方式1的半导体封装件10,但通过设置于粘接层110的开口部来实现对准标记114,在这一点上不同于半导体封装件10。在半导体封装件20中,在支承基材100未形成凹部。但是,也可以与半导体封装件10相同,在半导体封装件20的支承基材100设置凹部,并形成辅助对准标记。由于半导体封装件20的其他部件与半导体封装件10相同,因此在此省略详细说明。
(半导体封装件20的制造方法)
利用图25至图29,对本发明的实施方式2的半导体封装件20的制造方法进行说明。在图25至图29中,对于与图24所示的要素相同的要素赋予相同的附图标记。在以下说明中,对半导体封装件的制造方法进行说明,其中,与半导体封装件10相同,作为支承基材100使用SUS基材,作为第一树脂绝缘层130使用环氧类树脂,作为第一导电层142和第二导电层144使用Cu,作为焊料球160使用所述Sn合金,来制造半导体封装件。
图25为示出在本发明的一个实施方式的半导体封装件的制造方法中,准备支承基材的工序的图。在半导体封装件20的制造方法中,不在支承基材100形成对准标记。但是可以根据需要,利用与图2所示的制造方法相同的方法来形成对准标记。
图26为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材形成粘接层的工序的图。如图26所示,在支承基材100的上部面形成粘接层110。作为粘接层110粘贴片状粘接层。也可以利用涂敷法涂覆处于溶解于溶剂的状态的粘接层材料来形成粘接层110。
图27为示出在本发明的一个实施方式的半导体封装件的制造方法中,对支承基材的背面和侧面进行粗化的工序的图。为了抑制在后续工序中利用无电解镀敷法形成的镀层的剥离,将支承基材100的背面及侧面粗化(或粗面化)。可以使用含有Cu的化学溶液(蚀刻液)来进行支承基材100的粗化。在图27中,用虚线表示粗化区域104。
在此,例示了在粘贴粘接层110之后进行SUS基材的粗化的制造方法,但不限于此制造方法。例如,可以在粘贴粘接层110之前进行粗化。
图28为示出在本发明的一个实施方式的半导体封装件的制造方法中,在粘接层上形成对准标记的工序的图。对准标记114利用光刻及蚀刻来形成。对准标记114的位置及平面形状可以根据目的适当决定。在对准标记114设置为具有当利用光学显微镜等从上部面侧观察支承基材100时,能够视觉辨识的程度的高度差即可。即,图28的对准标记114是将粘接层110开口,但对准标记114可以为形成于粘接层110的凹部。在该工序中,可以在粘接层110加工除了对准标记114之外的开口部或凹部。可以通过基于激光照射的升华或烧蚀来去除粘接层110。或者,可以利用光刻及蚀刻来形成。
图29为示出在本发明的一个实施方式的半导体封装件的制造方法中,在支承基材上配置半导体装置的工序的图。基于如上所述地形成于粘接层的对准标记114来进行位置对准,并通过粘接层110将上部面设置有外部端子122的半导体装置120配置于支承基材100。可以利用例如,光学显微镜、CCD摄像机及电子显微镜等的方法来读取对准标记114。通过这些方法,能够以高对准精度来实现半导体装置120的安装。
以下的工序可以利用与图7至图23相同的制造方法来形成半导体封装件20。因此,省略对后续工序的说明。
[实施例]
以下,对在本发明的实施方式的半导体封装件的制造方法中,对示出实施例的电子显微镜图像(SEM图像)进行说明。具体地,关于如图11所示地对形成于第一树脂绝缘层130的开口部132进行等离子处理之后的样品的SEM图像及进行化学溶液处理之后的样品的SEM图像,进行说明。
图30为示出在本发明的一个实施例中的树脂绝缘层的开口部中进行残渣去除处理之前和之后的电子显微镜图像的图。在实施例中,作为第一树脂绝缘层130使用环氧类树脂。使用了CO2激光加工机来形成开口部132。作为开口部132的底部的残渣去除处理采用等离子处理及化学溶液处理。作为等离子处理进行包含CF4气及O2气的等离子处理,作为化学溶液处理,使用二甘醇单丁醚及乙二醇(溶胀溶液)、过锰酸钠(蚀刻液)及硫酸羟胺。
图30的(a)部分为在所述等离子处理之后的开口部132的底部的斜视SEM图像。如图30的(a)部分的箭头所示,在等离子处理之后球状的填料残留于开口部132的底部。图30的(b)部分为在所述等离子处理之后进行化学溶液处理之后的开口部132的底部的斜视SEM图像。如图30的(b)部分所示,在化学溶液处理之后开口部132的底部的残渣被去除。
如上所述,根据实施例1,可以确认:在形成开口部132之后,利用等离子处理及化学溶液处理这两个步骤处理,能够可靠地去除开口部132的底部的残渣。
此外,本发明不限于上述实施方式,可以在不脱离要旨的范围内适当进行变更。
Claims (20)
1.一种半导体封装件的制造方法,其特征在于,包括如下步骤:
在基材上配置上部面设有外部端子的半导体装置;
形成覆盖所述半导体装置的树脂绝缘层;
在所述树脂绝缘层形成用于露出所述外部端子的开口部;
在形成所述开口部之后,对所述开口部的底部进行等离子处理;
在所述等离子处理之后,对所述开口部的底部进行化学溶液处理;以及
形成与在所述开口部中露出的所述外部端子相连接的导体。
2.根据权利要求1所述的半导体封装件的制造方法,其特征在于,所述树脂绝缘层具有填料。
3.根据权利要求2所述的半导体封装件的制造方法,其特征在于,所述填料包含无机材料。
4.根据权利要求3所述的半导体封装件的制造方法,其特征在于,所述等离子处理为包含氟和氧的处理。
5.根据权利要求4所述的半导体封装件的制造方法,其特征在于,所述化学溶液处理是利用包含钾和锰的碱性化学溶液的处理或包含钠和锰的碱性化学溶液的处理。
6.根据权利要求3所述的半导体封装件的制造方法,其特征在于,所述化学溶液处理包括如下处理:
使所述树脂绝缘层溶胀;
对溶胀的所述树脂绝缘层进行蚀刻;以及
中和所述蚀刻所使用的化学溶液。
7.根据权利要求6所述的半导体封装件的制造方法,其特征在于,所述蚀刻为使用包含钾和锰的碱性化学溶液的处理或包含钠和锰的碱性化学溶液的处理。
8.根据权利要求5所述的半导体封装件的制造方法,其特征在于,通过对所述树脂绝缘层照射激光来形成所述开口部。
9.根据权利要求8所述的半导体封装件的制造方法,其特征在于,
在所述树脂绝缘层上形成导电层,
利用所述激光来一并加工所述导电层和所述树脂绝缘层。
10.根据权利要求9所述的半导体封装件的制造方法,其特征在于,
对所述导电层的表面进行粗面化处理;
利用所述激光来加工经过所述粗面化处理的所述导电层。
11.根据权利要求6所述的半导体封装件的制造方法,其特征在于,通过对所述树脂绝缘层照射激光来形成所述开口部。
12.根据权利要求11所述的半导体封装件的制造方法,其特征在于,
在所述树脂绝缘层上形成导电层;
利用所述激光来一并加工所述导电层和所述树脂绝缘层。
13.根据权利要求12所述的半导体封装件的制造方法,其特征在于,
对所述导电层的表面进行粗面化处理,
利用所述激光来加工经过所述粗面化处理的所述导电层。
14.根据权利要求7所述的半导体封装件的制造方法,其特征在于,通过对所述树脂绝缘层照射激光来形成所述开口部。
15.根据权利要求14所述的半导体封装件的制造方法,其特征在于,
在所述树脂绝缘层上形成导电层,
利用所述激光来一并加工所述导电层和所述树脂绝缘层。
16.根据权利要求15所述的半导体封装件的制造方法,其特征在于,
对所述导电层的表面进行粗面化处理,
利用所述激光来加工经过所述粗面化处理的所述导电层。
17.根据权利要求1所述的半导体封装件的制造方法,其特征在于,所述等离子处理为包含氟和氧的处理。
18.根据权利要求17所述的半导体封装件的制造方法,其特征在于,所述化学溶液处理为利用包含钾和锰的碱性化学溶液的处理或包含钠和锰的碱性化学溶液的处理。
19.根据权利要求1所述的半导体封装件的制造方法,其特征在于,通过对所述树脂绝缘层照射激光来形成所述开口部。
20.根据权利要求19所述的半导体封装件的制造方法,其特征在于,包括如下步骤:
在所述树脂绝缘层上形成导电层;
对所述导电层的表面进行粗面化处理;以及
利用所述激光来加工经过所述粗面化处理的所述导电层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016090193A JP2017199824A (ja) | 2016-04-28 | 2016-04-28 | 半導体パッケージの製造方法 |
JP2016-090193 | 2016-04-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN107342236A true CN107342236A (zh) | 2017-11-10 |
Family
ID=60158515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710239394.XA Pending CN107342236A (zh) | 2016-04-28 | 2017-04-13 | 半导体封装件的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10096564B2 (zh) |
JP (1) | JP2017199824A (zh) |
KR (1) | KR20170123241A (zh) |
CN (1) | CN107342236A (zh) |
TW (1) | TW201802967A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111512431A (zh) * | 2017-12-22 | 2020-08-07 | 美光科技公司 | 用于预防焊料桥接的互连结构及相关系统及方法 |
CN114407455A (zh) * | 2021-12-29 | 2022-04-29 | 沈阳和研科技有限公司 | 小颗粒电子封装材料加工用复合夹层结构及其加工方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080007927A1 (en) * | 2005-12-16 | 2008-01-10 | Ibiden Co., Ltd. | Multilayered printed circuit board and the manufacturing method thereof |
US20090288870A1 (en) * | 2008-05-25 | 2009-11-26 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
JP2013251368A (ja) * | 2012-05-31 | 2013-12-12 | Hitachi Chemical Co Ltd | 半導体装置の製造方法及びそれに用いる熱硬化性樹脂組成物並びにそれにより得られる半導体装置 |
US20140209361A1 (en) * | 2013-01-31 | 2014-07-31 | Kyocera Slc Technologies Corporation | Wiring board and method for manufacturing the same |
CN105206588A (zh) * | 2014-06-19 | 2015-12-30 | 株式会社吉帝伟士 | 半导体封装件及其制造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005159330A (ja) * | 2003-11-05 | 2005-06-16 | Hitachi Chem Co Ltd | 多層回路基板の製造方法及びこれから得られる多層回路基板、半導体チップ搭載基板並びにこの基板を用いた半導体パッケージ |
JP5419441B2 (ja) * | 2008-12-26 | 2014-02-19 | 富士フイルム株式会社 | 多層配線基板の形成方法 |
JP2010278334A (ja) | 2009-05-29 | 2010-12-09 | Elpida Memory Inc | 半導体装置 |
JP5903337B2 (ja) * | 2012-06-08 | 2016-04-13 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
WO2015151935A1 (ja) * | 2014-03-31 | 2015-10-08 | 三井金属鉱業株式会社 | キャリア箔付銅箔、銅張積層板及びプリント配線板 |
JP2016035969A (ja) * | 2014-08-01 | 2016-03-17 | 味の素株式会社 | 回路基板及びその製造方法 |
-
2016
- 2016-04-28 JP JP2016090193A patent/JP2017199824A/ja not_active Withdrawn
-
2017
- 2017-04-07 US US15/481,848 patent/US10096564B2/en active Active
- 2017-04-13 CN CN201710239394.XA patent/CN107342236A/zh active Pending
- 2017-04-14 TW TW106112542A patent/TW201802967A/zh unknown
- 2017-04-17 KR KR1020170048961A patent/KR20170123241A/ko unknown
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080007927A1 (en) * | 2005-12-16 | 2008-01-10 | Ibiden Co., Ltd. | Multilayered printed circuit board and the manufacturing method thereof |
CN101331814A (zh) * | 2005-12-16 | 2008-12-24 | 揖斐电株式会社 | 多层印刷线路板及其制造方法 |
US20090288870A1 (en) * | 2008-05-25 | 2009-11-26 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same |
JP2013251368A (ja) * | 2012-05-31 | 2013-12-12 | Hitachi Chemical Co Ltd | 半導体装置の製造方法及びそれに用いる熱硬化性樹脂組成物並びにそれにより得られる半導体装置 |
US20140209361A1 (en) * | 2013-01-31 | 2014-07-31 | Kyocera Slc Technologies Corporation | Wiring board and method for manufacturing the same |
CN105206588A (zh) * | 2014-06-19 | 2015-12-30 | 株式会社吉帝伟士 | 半导体封装件及其制造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111512431A (zh) * | 2017-12-22 | 2020-08-07 | 美光科技公司 | 用于预防焊料桥接的互连结构及相关系统及方法 |
CN111512431B (zh) * | 2017-12-22 | 2024-04-05 | 美光科技公司 | 用于预防焊料桥接的互连结构及相关系统及方法 |
CN114407455A (zh) * | 2021-12-29 | 2022-04-29 | 沈阳和研科技有限公司 | 小颗粒电子封装材料加工用复合夹层结构及其加工方法 |
CN114407455B (zh) * | 2021-12-29 | 2023-08-18 | 沈阳和研科技股份有限公司 | 小颗粒电子封装材料加工用复合夹层结构及其加工方法 |
Also Published As
Publication number | Publication date |
---|---|
US10096564B2 (en) | 2018-10-09 |
KR20170123241A (ko) | 2017-11-07 |
JP2017199824A (ja) | 2017-11-02 |
TW201802967A (zh) | 2018-01-16 |
US20170317045A1 (en) | 2017-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107424980A (zh) | 半导体封装件及半导体封装件的制造方法 | |
CN107424960A (zh) | 半导体封装件及半导体封装件的制造方法 | |
TWI229435B (en) | Manufacture of semiconductor device | |
CN107527825A (zh) | 半导体封装件的制造方法 | |
CN102468186A (zh) | 基板的制作方法及半导体芯片的封装方法 | |
CN107507779A (zh) | 半导体封装件的制造方法 | |
CN107342236A (zh) | 半导体封装件的制造方法 | |
WO2019071012A1 (en) | INDUSTRIAL CHIP LIGHT ENCLOSURE FOR MICROELECTRONIC DEVICE | |
CN101656241B (zh) | 具有基板支柱的封装结构及其封装方法 | |
TW200534428A (en) | Electrical connection structure of embedded chip and method for fabricating the same | |
TW201019810A (en) | Low-temperature recoverable electronic component | |
CN109075375A (zh) | 微电池的简化气密包装 | |
US9929069B2 (en) | Semiconductor device and manufacturing method thereof | |
CN109219236A (zh) | 透明柔性电路板及其制备方法 | |
JP2009302160A (ja) | 半導体装置製造方法および半導体装置 | |
CN104981092A (zh) | 表面镀层和包括该表面镀层的半导体封装件 | |
CN104347494A (zh) | 硅通孔金属柱背面互联方法 | |
JP2008258552A (ja) | 半導体チップ積層実装体の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Oita Prefecture Applicant after: Rely on Technology Japan company Address before: Oita Prefecture Applicant before: J-DEVICES Corp. |
|
CB02 | Change of applicant information | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20171110 |
|
WD01 | Invention patent application deemed withdrawn after publication |