JP5467471B2 - 離間された導電配線に電気的接続を提供する方法 - Google Patents
離間された導電配線に電気的接続を提供する方法 Download PDFInfo
- Publication number
- JP5467471B2 JP5467471B2 JP2012511906A JP2012511906A JP5467471B2 JP 5467471 B2 JP5467471 B2 JP 5467471B2 JP 2012511906 A JP2012511906 A JP 2012511906A JP 2012511906 A JP2012511906 A JP 2012511906A JP 5467471 B2 JP5467471 B2 JP 5467471B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- mask
- landing pad
- contact landing
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 106
- 239000000463 material Substances 0.000 claims description 191
- 229920001400 block copolymer Polymers 0.000 claims description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 239000011810 insulating material Substances 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 22
- 230000008021 deposition Effects 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 18
- 238000005520 cutting process Methods 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 13
- 238000007772 electroless plating Methods 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 238000000231 atomic layer deposition Methods 0.000 claims 2
- 238000010292 electrical insulation Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 24
- 239000011159 matrix material Substances 0.000 description 18
- 239000010410 layer Substances 0.000 description 16
- 238000000206 photolithography Methods 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000000059 patterning Methods 0.000 description 11
- 229920000642 polymer Polymers 0.000 description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 7
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 7
- 239000004926 polymethyl methacrylate Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000001338 self-assembly Methods 0.000 description 6
- 239000004793 Polystyrene Substances 0.000 description 5
- 230000006911 nucleation Effects 0.000 description 5
- 238000010899 nucleation Methods 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 229920002223 polystyrene Polymers 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 125000002524 organometallic group Chemical group 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- -1 for example Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000255925 Diptera Species 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 238000004043 dyeing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008014 freezing Effects 0.000 description 1
- 238000007710 freezing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 239000012266 salt solution Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06137—Square or rectangular array with specially adapted redistribution layers [RDL]
- H01L2224/06138—Square or rectangular array with specially adapted redistribution layers [RDL] being disposed in a single wiring level, i.e. planar layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (40)
- 支持構造上に集積回路構造を製造する方法であって、
少なくとも1つの材料からなる複数の直線的に延在する材料配線を形成することと、
前記材料配線を、直線的に延在する方向に対して角度を付けて切断して、前記材料配線の各々にそれぞれの斜端面を形成することであって、前記ぞれぞれの斜端面が前記直線的に延在する方向に離間される、ことと、
それぞれの斜端面の各々に、前記材料配線の各々の各拡張部を個々に形成することと、
を含むことを特徴とする方法。 - 前記材料配線は、平行な材料配線であることを特徴とする請求項1に記載の方法。
- 前記平行な材料配線の前記斜端面を同時に形成するために、前記斜端面がマスク及びエッチング工程を用いて切断されることを特徴とする請求項2に記載の方法。
- 前記角度は、前記直線的に延在する方向に対して5度と30度との間であることを特徴とする請求項2に記載の方法。
- 前記平行な材料配線は、45nm以下のハーフピッチを有することを特徴とする請求項2に記載の方法。
- 前記平行な材料配線は、20nm以下のハーフピッチを有することを特徴とする請求項2に記載の方法。
- 前記平行な材料配線は、自己組織化されたブロックコポリマーマスクを用いて形成されることを特徴とする請求項2に記載の方法。
- 前記平行な材料配線を切断することに先立って、封入絶縁材料で前記平行な材料配線を被覆することを更に含むことを特徴とする請求項2に記載の方法。
- 前記拡張部は、前記それぞれの斜端面でのパッド材料の選択的堆積によって成長させることを特徴とする請求項1に記載の方法。
- 前記平行な材料配線及びそれぞれの拡張部をエッチマスクとして用いて、前記平行な材料配線及びそれぞれの拡張部の下に設けられた導電材料をエッチングして、それぞれの電気的コンタクトランディングパッド領域を有する導電配線を形成することを更に含むことを特徴とする請求項2に記載の方法。
- 前記少なくとも1つの材料が、フォトレジスト、ブロックコポリマー、シリコン、ポリシリコン、及び金属のうちの1つであることを特徴とする請求項10に記載の方法。
- 前記少なくとも1つの材料は、処理されたブロックコポリマーであり、かつ、
前記平行な材料配線及びそれぞれの拡張部をエッチマスクとして用いて、前記平行な材料配線及びそれぞれの拡張部の下に設けられたマスク材料をエッチングして、マスクパターンを形成することと、
前記マスクパターンを第2のエッチマスクとして用いて、前記マスクパターンの下に設けられた導電材料をエッチングして、それぞれの電気的コンタクトランディングパッドを有する導電配線を形成することと、
を更に含むことを特徴とする請求項2に記載の方法。 - 前記少なくとも1つの材料が少なくとも1つの導電材料を含み、かつ、前記拡張部が導電性コンタクトランディングパッドであることを特徴とする請求項1に記載の方法。
- 前記導電材料は、金属、金属シリサイド、及びポリシリコンのうちの少なくとも1つを含むことを特徴とする請求項13に記載の方法。
- 前記斜端面に露出された導電材料が、前記斜端面での導電材料の選択的堆積によって前記導電性コンタクトランディングパッドを成長させるためのシードとして用いられることを特徴とする請求項13に記載の方法。
- 集積回路構造を製造する方法であって、
複数の平行な離間した直線的に延在する材料配線を形成することと、
前記材料配線の直線的に延在する方向に対して角度を付けて前記材料配線をエッチングして、前記平行な材料配線の各々にそれぞれの斜端面を形成することであって、前記ぞれぞれの斜端面が前記直線的に延在する方向に離間される、ことと、
前記斜端面の各々に接触する各コンタクトランディングパッドマスクを個々に形成することと、
前記材料配線及び前記コンタクトランディングパッドマスクをエッチマスクとして用いて、前記材料配線及び前記コンタクトランディングパッドマスクの下の導電材料をエッチングして、それぞれの導電性コンタクトランディングパッド領域を有する、45nm以下のハーフピッチを有する複数の導電配線を形成することと、
を含むことを特徴とする方法。 - 前記材料配線をエッチングすることに先立って、封入絶縁材料で前記材料配線を被覆することを更に含むことを特徴とする請求項16に記載の方法。
- 前記平行な材料配線の前記斜端面を同時に形成するために、前記斜端面がマスク及びエッチング工程を用いて切断されることを特徴とする請求項16に記載の方法。
- 前記角度は、前記直線的に延在する方向に対して5度と30度との間であることを特徴とする請求項16に記載の方法。
- 前記導電配線は、20nm以下のハーフピッチを有することを特徴とする請求項16に記載の方法。
- 前記材料配線が、処理されたフォトレジスト、処理されたブロックコポリマー、シリコン、ポリシリコン、及び金属のうちの1つであることを特徴とする請求項16に記載の方法。
- 前記各コンタクトランディングパッドマスクを形成することは、
前記斜端面における前記材料配線の少なくとも一部をシードとして用いることと、
拡張材料の選択的堆積によって、前記シードから前記コンタクトランディングパッドマスクを成長させることと、
を含むことを特徴とする請求項16に記載の方法。 - 前記選択的堆積は、化学蒸着、原子層蒸着、無電解メッキ、又はエピタキシャル成長のうちの1つであることを特徴とする請求項22の方法。
- 前記導電性コンタクトランディングパッド領域は、前記それぞれの導電配線との電気的接続のための領域を形成するのに十分な大きさであるが、それぞれの導電性コンタクトランディングパッド領域間の電気的絶縁を提供するのに十分な間隔で離間されることを特徴とする請求項16に記載の方法。
- 集積回路構造を製造する方法であって、
複数の平行な離間した直線的に延在する導電配線を形成することと、
前記導電配線の直線的に延在する方向に対して角度を付けて前記導電配線をエッチングして、前記導電配線の各々にそれぞれの斜端面を形成することであって、前記ぞれぞれの斜端面が、前記直線的に延在する方向に離間される、ことと、
前記それぞれの斜端面の各々に接触する各電気的コンタクトランディングパッドを個々に形成することと、
を含むことを特徴とする方法。 - 前記導電配線を切断することに先立って、封入絶縁材料で前記導電配線を被覆することを更に含むことを特徴とする請求項25に記載の方法。
- 前記平行な導電配線の斜端面を同時に形成するために、前記斜端面がマスク及びエッチング工程を用いて切断されることを特徴とする請求項25に記載の方法。
- 前記角度は、前記直線的に延在する方向に対して5度と30度との間であることを特徴とする請求項25に記載の方法。
- 前記導電配線は、20nm以下のハーフピッチを有することを特徴とする請求項25に記載の方法。
- 前記導電配線の少なくとも1つの層は、金属、金属シリサイド、及びポリシリコンのうちの少なくとも1つを含むことを特徴とする請求項25に記載の方法。
- 前記電気的コンタクトランディングパッドは、
前記斜端面における前記導電配線の少なくとも一部をシードとして用いることと、
導電材料の選択的堆積によって、前記シードから前記電気的コンタクトランディングパッドを成長させることと、
によって形成されることを特徴とする請求項25に記載の方法。 - 前記選択的堆積は、化学蒸着、原子層蒸着、無電解メッキ、又はエピタキシャル成長のうちの1つであることを特徴とする請求項31の方法。
- 前記電気的コンタクトランディングパッドは、前記それぞれの導電配線との電気的接続のための領域を形成するのに十分な大きさであるが、前記それぞれの電気的コンタクトランディングパッド間の電気的絶縁を提供するのに十分な間隔で離間されることを特徴とする請求項25に記載の方法。
- 集積回路であって、
前記集積回路の一部として形成された、複数の平行な直線的に延在する導電配線であって、前記導電配線の各々が、前記導電配線の直線的に延在する方向に沿った異なる位置に斜端面を有する、導電配線と、
各斜端面に電気的に接触して個々に形成された各コンタクトランディングパッドと、
を具備することを特徴とする集積回路。 - 前記導電配線は、45nm以下のハーフピッチを有することを特徴とする請求項34に記載の集積回路。
- 前記導電配線は、20nm以下のハーフピッチを有することを特徴とする請求項35に記載の集積回路。
- 前記斜端面の角度は、前記直線的に延在する方向に対して5度と30度との間であることを特徴とする請求項34に記載の集積回路。
- 前記導電配線は、ポリシリコン材料及び金属シリサイド材料を含むことを特徴とする請求項34に記載の集積回路。
- 前記導電配線は、金属材料を含むことを特徴とする請求項34に記載の集積回路。
- 前記導電配線は、メモリデバイスのワード線及びビット線のうちの少なくとも1つを形成することを特徴とする請求項34に記載の集積回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/469,495 US8043964B2 (en) | 2009-05-20 | 2009-05-20 | Method for providing electrical connections to spaced conductive lines |
US12/469,495 | 2009-05-20 | ||
PCT/US2010/034831 WO2010135168A2 (en) | 2009-05-20 | 2010-05-14 | Method for providing electrical connections to spaced conductive lines |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012527773A JP2012527773A (ja) | 2012-11-08 |
JP5467471B2 true JP5467471B2 (ja) | 2014-04-09 |
Family
ID=43034611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012511906A Active JP5467471B2 (ja) | 2009-05-20 | 2010-05-14 | 離間された導電配線に電気的接続を提供する方法 |
Country Status (8)
Country | Link |
---|---|
US (6) | US8043964B2 (ja) |
EP (1) | EP2425449B1 (ja) |
JP (1) | JP5467471B2 (ja) |
KR (1) | KR101312758B1 (ja) |
CN (1) | CN102428554B (ja) |
SG (1) | SG175984A1 (ja) |
TW (1) | TWI415225B (ja) |
WO (1) | WO2010135168A2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8247904B2 (en) * | 2009-08-13 | 2012-08-21 | International Business Machines Corporation | Interconnection between sublithographic-pitched structures and lithographic-pitched structures |
WO2014050305A1 (ja) * | 2012-09-27 | 2014-04-03 | 株式会社 日立ハイテクノロジーズ | パターン計測装置、自己組織化リソグラフィに用いられる高分子化合物の評価方法、及びコンピュータープログラム |
US9053255B2 (en) | 2012-10-12 | 2015-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method of generating masks for making integrated circuit |
TWI494537B (zh) * | 2013-01-23 | 2015-08-01 | Hitachi High Tech Corp | A pattern measuring method, a device condition setting method of a charged particle beam device, and a charged particle beam device |
US9831062B2 (en) | 2013-01-23 | 2017-11-28 | Hitachi High-Technologies Corporation | Method for pattern measurement, method for setting device parameters of charged particle radiation device, and charged particle radiation device |
US9136168B2 (en) * | 2013-06-28 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive line patterning |
CN107833873A (zh) * | 2015-04-20 | 2018-03-23 | 江苏时代全芯存储科技有限公司 | 记忆体结构与其制备方法 |
US9559086B2 (en) * | 2015-05-29 | 2017-01-31 | Micron Technology, Inc. | Semiconductor device with modified current distribution |
US9911693B2 (en) * | 2015-08-28 | 2018-03-06 | Micron Technology, Inc. | Semiconductor devices including conductive lines and methods of forming the semiconductor devices |
US9735157B1 (en) | 2016-03-18 | 2017-08-15 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US10818505B2 (en) * | 2018-08-15 | 2020-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned double patterning process and semiconductor structure formed using thereof |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3881244A (en) * | 1972-06-02 | 1975-05-06 | Texas Instruments Inc | Method of making a solid state inductor |
US5243208A (en) * | 1987-05-27 | 1993-09-07 | Hitachi, Ltd. | Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array |
US5336921A (en) * | 1992-01-27 | 1994-08-09 | Motorola, Inc. | Vertical trench inductor |
US5378649A (en) * | 1994-04-08 | 1995-01-03 | United Microelectronics Corporation | Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas |
JPH10116829A (ja) * | 1996-10-08 | 1998-05-06 | Oki Electric Ind Co Ltd | 半導体装置における多層配線 |
JP2000019709A (ja) * | 1998-07-03 | 2000-01-21 | Hitachi Ltd | 半導体装置及びパターン形成方法 |
US6614093B2 (en) * | 2001-12-11 | 2003-09-02 | Lsi Logic Corporation | Integrated inductor in semiconductor manufacturing |
US7413833B2 (en) * | 2004-05-14 | 2008-08-19 | Infineon Technologies Ag | Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask |
JP2006173186A (ja) * | 2004-12-13 | 2006-06-29 | Toshiba Corp | 半導体装置、パターンレイアウト作成方法および露光マスク |
KR100718216B1 (ko) * | 2004-12-13 | 2007-05-15 | 가부시끼가이샤 도시바 | 반도체 장치, 패턴 레이아웃 작성 방법, 노광 마스크 |
JP4936659B2 (ja) * | 2004-12-27 | 2012-05-23 | 株式会社東芝 | 半導体装置の製造方法 |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
JP2006310707A (ja) * | 2005-05-02 | 2006-11-09 | Toshiba Corp | パターン形成方法 |
US20070045698A1 (en) * | 2005-08-31 | 2007-03-01 | International Business Machines Corporation | Semiconductor structures with body contacts and fabrication methods thereof |
US7611980B2 (en) * | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
WO2009031052A2 (en) * | 2007-03-29 | 2009-03-12 | Innovative Silicon S.A. | Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor |
US20090045061A1 (en) * | 2007-06-20 | 2009-02-19 | New Jersey Institute Of Technology | Nanotube Devices and Vertical Field Effect Transistors |
US7741721B2 (en) * | 2007-07-31 | 2010-06-22 | International Business Machines Corporation | Electrical fuses and resistors having sublithographic dimensions |
JP2009042660A (ja) * | 2007-08-10 | 2009-02-26 | Renesas Technology Corp | 半導体装置、フォトマスク、半導体装置の製造方法およびパターンレイアウト方法 |
US8735258B2 (en) * | 2012-01-05 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit resistor fabrication with dummy gate removal |
-
2009
- 2009-05-20 US US12/469,495 patent/US8043964B2/en active Active
-
2010
- 2010-05-14 JP JP2012511906A patent/JP5467471B2/ja active Active
- 2010-05-14 SG SG2011082781A patent/SG175984A1/en unknown
- 2010-05-14 WO PCT/US2010/034831 patent/WO2010135168A2/en active Application Filing
- 2010-05-14 KR KR1020117030490A patent/KR101312758B1/ko active IP Right Grant
- 2010-05-14 EP EP10724936.9A patent/EP2425449B1/en active Active
- 2010-05-14 CN CN201080022035.5A patent/CN102428554B/zh active Active
- 2010-05-20 TW TW099116174A patent/TWI415225B/zh active
-
2011
- 2011-09-19 US US13/235,939 patent/US8383504B2/en active Active
-
2013
- 2013-01-28 US US13/751,781 patent/US8629051B2/en active Active
- 2013-12-04 US US14/096,052 patent/US8735285B2/en active Active
-
2014
- 2014-04-22 US US14/258,476 patent/US8987906B2/en active Active
-
2015
- 2015-02-27 US US14/633,189 patent/US9224742B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8629051B2 (en) | 2014-01-14 |
US20140225264A1 (en) | 2014-08-14 |
CN102428554A (zh) | 2012-04-25 |
WO2010135168A2 (en) | 2010-11-25 |
US8735285B2 (en) | 2014-05-27 |
US8383504B2 (en) | 2013-02-26 |
EP2425449A2 (en) | 2012-03-07 |
US20150171090A1 (en) | 2015-06-18 |
TWI415225B (zh) | 2013-11-11 |
CN102428554B (zh) | 2015-04-15 |
KR101312758B1 (ko) | 2013-09-27 |
SG175984A1 (en) | 2011-12-29 |
US9224742B2 (en) | 2015-12-29 |
KR20120024805A (ko) | 2012-03-14 |
US20140094026A1 (en) | 2014-04-03 |
TW201106448A (en) | 2011-02-16 |
US8987906B2 (en) | 2015-03-24 |
EP2425449B1 (en) | 2020-02-26 |
US8043964B2 (en) | 2011-10-25 |
US20130210230A1 (en) | 2013-08-15 |
US20120009784A1 (en) | 2012-01-12 |
US20100295183A1 (en) | 2010-11-25 |
JP2012527773A (ja) | 2012-11-08 |
WO2010135168A3 (en) | 2011-01-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5467471B2 (ja) | 離間された導電配線に電気的接続を提供する方法 | |
JP3406302B2 (ja) | 微細パターンの形成方法、半導体装置の製造方法および半導体装置 | |
JP5505904B2 (ja) | 二次元自己組織化サブリソグラフィ・ナノスケール構造およびこれを製造するための方法(自己組織化材料を用いた二次元パターニング) | |
TW201530692A (zh) | 使用消減技術形成之自對準互連 | |
TW200901278A (en) | Method of fabricating pattern in semiconductor device using spacer | |
TWI336101B (en) | Semiconductor device with a bulb-type recess gate and method for manufacturing the same | |
US20200090985A1 (en) | Self-aligned pattern formation for a semiconductor device | |
CN112447528A (zh) | 集成电路的制作方法 | |
CN112750773A (zh) | 生产接触晶体管的栅极和源极/漏极通孔连接的方法 | |
US11264271B2 (en) | Semiconductor fabrication method for producing nano-scaled electrically conductive lines | |
US10636658B1 (en) | Methods of forming patterns, and methods of patterning conductive structures of integrated assemblies | |
KR20090061162A (ko) | 반도체 소자의 제조 방법 | |
JP3328459B2 (ja) | 半導体装置の製造方法 | |
US20200185269A1 (en) | Self-aligned litho-etch double patterning | |
CN113725223A (zh) | 半导体工艺以及半导体结构 | |
JPH0387030A (ja) | 多層配線法 | |
TW200419724A (en) | Method for integrating memory cell array and periphery circuit in pitch reduction process | |
JPH08107111A (ja) | 半導体装置の製造方法 | |
KR20070105772A (ko) | 반도체 소자의 저항 형성방법 | |
JPH03224229A (ja) | 半導体装置の製造方法 | |
KR19990006002A (ko) | 반도체 소자의 도전층 제조방법 | |
JPS62104030A (ja) | 半導体装置の製造方法 | |
KR20070089530A (ko) | 반도체 소자의 패턴 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130905 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130910 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131118 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20131118 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131217 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140116 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5467471 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |