13 00^p^^84 19619twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體製程，且特別是有關於一 種具有兩種深度的隔離結構的製造方法。 【先前技術】 隨著積體電路晶片之㈣元件_集度（integrati〇n) 不斷地攀升，相鄰元件間不必要的電子互相干擾的可能性 _ 會增加。舉例而言，互補式金氧半場效電晶體 (complementary metal oxide semic〇nduct〇r，CM〇s )很容 易發生_現象（lateh，）’而且在高積缝的積體電路 中，此閂鎖現象會更嚴重。因此，積體電路必須具有適當 的隔離結構，以避免元件與元件互相干擾。 ” 在各種隔離結構巾’區域氧化法㈣成的隔離結構 (local oxidation of silicon ’ L0C0S )已經普遍應用在各種 積體電路。然而，因為區域氧化法會減少主動區（ φ area)的面積、降低元件的效能、並增加後續微影製程的 困難度，所以區域氧化法已逐漸被淺溝渠隔離結構 (shallow trench isolation，STI)取代。 一般而言，以較咼電壓操作的半導體元件的周圍必須 配置珠度較深的淺溝渠隔離結構。以記憶體的製程為例， 記憶胞區（memory cell area)與周邊電路區（periphery circuitry area)會形成不同深度的兩組淺溝渠隔離結構。目 前習知的具有兩種不同深度的淺溝渠隔離結構的製造方法 19619twf.doc/g I300»4 . · 如下所述。 方法一 g對基底進行兩次微影㈣㈣來形成不 度的兩組溝渠。然後，形成一層 同深 絕緣層在這兩組溝渠内。 !=r上述溝渠的深度。然後:形成:層： 追兩組溝渠内。 程’組溝渠:接著，進行第二次微影蝕i製程 緣層在 a# =二:知’在製造不同深度的兩組淺溝渠隔離結構 夺，卩 >兩要兩次微影蝕刻製程 會提 雜性並增加製造成本。 表枉的设 【發明内容】 有饈I於此，本發明之目的是提供一種隔離結構的製造 方法，此方法能夠以一次微影製程來製造雨組不同深度的 隔離結構，以降低製程的複雜性並降低製造成本。 為達上述或是其他目的，本發明提出一種隔離結構的 Φ 衣造方法。此方法是先提供基底。然後，圖案化基底，以 形成數個第一溝渠及第二溝渠。其中第一溝渠的寬度小於 第二溝渠的寬度。之後，於基底上形成一層共形的絕緣層。 接著’移除部分絕緣層，使殘餘的絕緣層填滿第一溝渠， 並在於第二溝渠的側壁上形成數個間隙壁。之後，移除這 些間隙壁之間的第二溝渠底部的部分基底，使第二溝渠的 深度大於第一溝渠的深度。繼之，於第一溝渠及第二溝渠 中形成一層介電層。 13〇〇9麟84 19619twf.doc/g 在本發明之一實施例中，圖案化上述之基底的方法包 括在基底上形成一層第一罩幕層。之後，圖案化這一層第 一罩幕層，並移除暴露的基底。其中第一罩幕層的材質例 如是氮化矽，且形成第一罩幕層之前，更包括在基底上形 成一層墊氧化層（pad oxide)。在形成第一罩幕層之後， 更包括於第一罩幕層上形成一層第二罩幕層。此外，第二 單幕層的材質例如是硼矽玻璃（b⑽silicate glass，bsg)、 硼磷矽玻璃（b〇rophosphosilicate glass，BPSG)或多晶矽。 在本發明之一實施例中，於形成上述之介電層之前， 更包括移除殘餘的絕緣層、第一罩幕層、第二罩幕層及間 隙壁。移除殘餘的絕緣層、第二罩幕層及間隙壁的方法例 如是溼蝕刻製程。 在本發明之一實施例中，移除部分第一介電層之方法 例如疋非等向性餘刻法。 ^制為達上述或是其他目的，本發明再提出一種隔離結構 F衣k方法。此方法包括提供基底，基底可區分為記憶胞 邊電路區。祕，圖案化基底，以於記憶胞區形成 #弟一溝渠並於週邊電路區形成數個第二溝渠。其中些 Ci寬度小於第二溝渠的寬度。接著，於記憶胞區 、、蓋泪、滿第-溝渠的第—介電層，並於週邊電路區的第二 1側壁上形成數個間隙壁。之後，移除間隙壁之間的 底部的部分基底，使第二溝渠的深度大於第一溝 ί的。隨後，移除第—介電層及間隙壁，並於記憶胞 弟一溝渠及週邊電路_第二溝渠中形成-層第二介 84 19619twf.doc/g 電層。 泪，本發明之一實施例中，於記憶胞區形成填滿第一溝 木的第一介電層’並於週邊電路區的第二溝渠的侧壁上形 ^數個間隙壁的方法例如是先於基底上形成共形的一層絕 、、層、-層絕緣層填滿第一溝渠並覆蓋第二溝渠。然後， =非等向性_、製程移除部分絕緣層，而形成第一介電 曰，並在第二溝渠的侧壁上形成這些間隙壁。 ^發明之一實施例中，上述圖案化基底的方法例如 :底上喊-層第—罩幕層，然後圖案化第一罩幕 i二：的基底。其中第一罩幕層的材質例如 卜’在形成第一罩幕層之前，可以先於基底 开層塾氧化層。此外，在形成第—罩幕層 予 可以於第-罩幕層上形成—層第:w =例，侧、物玻璃或多;^ 二先移除殘餘的第-介電層、、第 不同深度的隔彡1^製造兩組 本。更詳細而言，本發明的製造方法低製造成 程的擇性地加深部分溝渠的深ΐ不使用微影製 易懂:、;文特χ二ί?和其他目的、特徵和優點能更明· 明如下y文特舉較佳貫施例’並配合所附圖式‘:二 13009j^^584 19619twf.doc/g 【實施方式】 有鑑於習知技術的缺點，本發明提供一種隔離結構的 製造方法。此製造方法是先在基底上形成兩組寬度不同的 溝渠。之後，在較寬的溝渠的側壁上形成間隙壁，同時， 間隙壁的材料會填滿較窄的溝渠。然後，利用自行對準 (self-aligned)的原理，以間隙壁為罩幕來移除間隙壁暴 露的部分基底，從而加深溝渠的深度。之後，形成一層介 電層在這兩組溝渠内，以形成隔離結構。 > 圖1至圖6是本發明一實施例的一種隔離結構的製造 方法剖面流程圖。 請參照圖1，首先提供基底1〇〇。基底1〇〇例如是石夕基 底。基底100例如可以分為第一區域102及第二區域1〇4。 本發明的隔離結構例如是應用於記憶體，其中第一區域 102例如疋§己憶胞區’且第二區域1 〇4例如是周邊電路區。 在本實施例中，第一區域102及第二區域1〇4的基底100 中將形成兩種不同深度的隔離結構。其中第二區域1〇4的 , 隔離結構的深度較深。隔離結構是以淺溝渠隔離結構為 例。然而本發明並不以此為限，隔離結構也包括深溝渠隔 離結構（deep trench isolation)或類似的其他隔離結構。 接者，依序在基底100上形成一層墊氧化層、一 層罩幕層108及一層罩幕層110。其中墊氧化層1〇6的材 質例如是氧化矽，墊氧化層106的形成方法例如是熱氧化 法。罩幕層108的材質例如是氮化石夕，罩幕層的形成 方法例如是化學氣相沈積法。罩幕層Π0的材質例如是石朋 13〇〇9絲84 19619twf.doc/g13 00^p^^84 19619twf.doc/g IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor process, and more particularly to a method of fabricating an isolation structure having two depths . [Prior Art] As the (integrated component) of the integrated circuit chip continuously rises, the possibility that unnecessary electrons between adjacent components interfere with each other _ will increase. For example, a complementary metal oxide semic〇nduct〇r (CM〇s) is prone to occur (lateh,) and is latched in a high-stack integrated circuit. The phenomenon will be more serious. Therefore, the integrated circuit must have an appropriate isolation structure to avoid interference between components and components. The local oxidation of silicon 'L0C0S' has been widely applied to various integrated circuits in various isolation structures. However, because the area oxidation method reduces the area of the active area (φ area) and reduces it. The efficiency of the component and the difficulty of the subsequent lithography process have led to the replacement of the shallow trench isolation (STI) by the regional trenching method. In general, the semiconductor components operating at a higher voltage must be arranged around the semiconductor device. A shallow trench isolation structure with deeper beading. Taking the memory process as an example, a memory cell area and a peripheral circuitry area form two sets of shallow trench isolation structures of different depths. Method for manufacturing shallow trench isolation structures with two different depths 19619twf.doc/g I300»4 . · As described below. Method 1 g performs two lithography (4) (4) on the substrate to form two groups of ditches. Then, Form a layer of the same deep insulation layer in the two groups of trenches. !=r The depth of the above-mentioned trenches. Then: Form: Layer: Chasing the two groups of trenches. 'Group ditch: Next, carry out the second micro-etching i process edge layer in a# = two: know 'in the manufacture of two sets of shallow trench isolation structures at different depths, 卩> two times two lithography etching process will mention Hybridity and increase manufacturing cost. The present invention aims to provide a method for manufacturing an isolation structure capable of manufacturing different depths of rain groups by one lithography process. Structure to reduce the complexity of the process and reduce the manufacturing cost. To achieve the above or other purposes, the present invention provides a Φ coating method for the isolation structure. The method is to provide a substrate first. Then, the substrate is patterned to form a plurality of a first trench and a second trench, wherein the width of the first trench is smaller than the width of the second trench. Thereafter, a conformal insulating layer is formed on the substrate. Then, a portion of the insulating layer is removed to fill the remaining insulating layer. a trench, and a plurality of spacers are formed on the sidewall of the second trench. Thereafter, a portion of the base of the bottom of the second trench between the spacers is removed to make the depth of the second trench In the depth of the first trench, a dielectric layer is formed in the first trench and the second trench. 13〇〇9麟84 19619twf.doc/g In an embodiment of the invention, the substrate is patterned The method includes forming a first mask layer on the substrate. Thereafter, patterning the first mask layer and removing the exposed substrate, wherein the material of the first mask layer is, for example, tantalum nitride, and forms the first Before a mask layer, a pad oxide is formed on the substrate. After forming the first mask layer, a second mask layer is further formed on the first mask layer. Further, the material of the second single curtain layer is, for example, b (10) silicate glass (bsg), b〇rophosphosilicate glass (BPSG) or polycrystalline germanium. In an embodiment of the invention, before the forming the dielectric layer, the residual insulating layer, the first mask layer, the second mask layer and the gap wall are further removed. The method of removing the residual insulating layer, the second mask layer, and the spacers is, for example, a wet etching process. In one embodiment of the invention, a method of removing a portion of the first dielectric layer is, for example, a non-isotropic remnant method. In order to achieve the above or other purposes, the present invention further proposes a method of isolating the structure. The method includes providing a substrate that can be distinguished as a memory cell side circuit region. Secret, patterned base, in the memory cell formation #弟一沟渠 and formed several second ditches in the peripheral circuit area. Some of these Ci widths are smaller than the width of the second trench. Next, in the memory cell region, the tear-drain, the first dielectric layer of the D-ditch, and a plurality of spacers are formed on the second sidewall of the peripheral circuit region. Thereafter, a portion of the base at the bottom between the spacers is removed such that the depth of the second trench is greater than that of the first trench. Subsequently, the first dielectric layer and the spacer are removed, and a second layer is formed in the memory cell-ditch and the peripheral circuit_second trench 84 19619twf.doc/g. In one embodiment of the present invention, a method of forming a first dielectric layer filling the first trench in the memory cell region and forming a plurality of spacers on the sidewall of the second trench in the peripheral circuit region is, for example, A first layer of insulating layer, a layer, and a layer of insulating layer formed on the substrate to fill the first trench and cover the second trench. Then, the non-isotropic _, the process removes a portion of the insulating layer to form a first dielectric yoke, and these spacers are formed on the sidewalls of the second trench. In one embodiment of the invention, the method of patterning the substrate is as follows: a shrub-layer-mask layer on the bottom, and then patterning the substrate of the first mask. The material of the first mask layer, for example, may be opened before the first mask layer is formed. In addition, the formation of the first mask layer can be formed on the first mask layer - the layer: w = for example, the side, the object glass or more; ^ two first remove the residual first - dielectric layer, the first difference The depth of the barrier 1 ^ manufacture two sets of books. In more detail, the manufacturing method of the present invention has a low manufacturing process to deepen the depth of a part of the trench without using the micro-shadow system to understand:, and the other purposes, features and advantages are more obvious. · The following is a description of the preferred embodiment 'and with the accompanying drawings': two 13009j^^584 19619twf.doc / g [Embodiment] In view of the shortcomings of the prior art, the present invention provides an isolation structure Production method. This manufacturing method is to first form two sets of trenches having different widths on the substrate. Thereafter, a spacer is formed on the sidewall of the wider trench, and at the same time, the material of the spacer fills the narrow trench. Then, using the self-aligned principle, the spacer is used as a mask to remove part of the substrate exposed by the spacer, thereby deepening the depth of the trench. Thereafter, a dielectric layer is formed in the two sets of trenches to form an isolation structure. > Fig. 1 to Fig. 6 are cross-sectional flow charts showing a method of manufacturing an isolation structure according to an embodiment of the present invention. Referring to Figure 1, the substrate 1 is first provided. The substrate 1 is, for example, a stone base. The substrate 100 can be divided, for example, into a first region 102 and a second region 1〇4. The isolation structure of the present invention is applied, for example, to a memory in which the first region 102 is, for example, a cell region' and the second region 1 is, for example, a peripheral circuit region. In this embodiment, two different depth isolation structures are formed in the substrate 100 of the first region 102 and the second region 1〇4. Where the second area is 1〇4, the depth of the isolation structure is deep. The isolation structure is exemplified by a shallow trench isolation structure. However, the invention is not limited thereto, and the isolation structure also includes deep trench isolation or the like. Then, a pad oxide layer, a mask layer 108 and a mask layer 110 are formed on the substrate 100 in sequence. The material of the pad oxide layer 1〇6 is, for example, ruthenium oxide, and the method of forming the pad oxide layer 106 is, for example, a thermal oxidation method. The material of the mask layer 108 is, for example, nitride nitride, and the mask layer is formed by, for example, chemical vapor deposition. The material of the mask layer Π0 is, for example, Shi Peng 13〇〇9 wire 84 19619twf.doc/g
石夕破璃、石朋石粦石夕玻璃或多曰 〇 ^ ^ 1 1 A 例如是化學氣相沈=曰夕’且罩幕層110的形成方法 然後’請參照圖2 ’圖案化罩幕層11〇，以形成罩幕 二Ξ案化罩幕層110的方法例如是利用光學微影製 :_幕"11G上形成—層_化光阻層。然後，以乾式 =J製程來移除暴露的罩幕層110。之後，移除上述』 :阻層。其中圖案化光阻層也可以在於 溝 渠後再移除。 风屏 卿幕層11Ga為罩幕，移除暴露的罩幕層108, ^成罩幕層職，並暴露純化層剛 =氧化層⑽’以形成塾氧化層廳a。其中，= 此外，9罩:化層:二的方法例如是乾式侧程。 罩幕層110a的功能是用來在基底1〇〇中形 ， 因此’只要罩幕層11Ga能夠達成此功戈了 方法都是可以的。 形成 而且，在另一實施例中’可以省略形成塾氧化層腸 =圖案化墊氧化層跑的步驟，或使用其他的^ 墊氧化層106及l〇6a。 木代曰 此外，在本實施例中，其以形成兩層材料不 層ll〇a、灌a為例作說明，當然在另一 只形成單一層罩幕層。 71 了以 繼之，請參照圖3，以罩幕層11〇&及1〇8 圖案化基底100以於第-區域1〇2中形成數個第巨 114,並於第二區域1()4中形成數個第二溝渠116。其中g 13009鯓 684 19619twf.doc/g 一溝渠114的寬度W1小於第二溝渠的寬度W2。圖案化 基底100的方法例如是乾式蝕刻製程。此外，本發明並不 限定圖案化基底100的方法。舉例而言，可以直接利用一 次微影製程及#刻製程來圖案化基底1〇〇，而不須先形成 罩幕層110a及108a。接著，在基底1〇〇上方形成一層共 形的絕緣層118。此絕緣層118填滿第一溝渠114，但是並 未填滿第二溝渠116。絕緣層118的材質例如是氧化矽， 且絕緣層118的形成方法例如是化學氣相沈積法。 然後，請參照圖4，移除部分的絕緣層118，以於第 二溝渠116的側壁上形成間隙壁n8a，其暴露第二區域1〇4 的第二溝渠116的底部。其中移除部分的絕緣層118的方 法例如疋乾式姓刻製程。此外，在本實施例中，第一區域 102的第一溝渠114的寬度W1小於第二區域1〇4的第一 ^渠y4的寬度W2。因此在上述乾式钱刻製程之後，於 第一區域々104白勺第二、溝$ 116的側壁上會形成間隙壁 118a且第一區域1〇2的第一溝渠丨丨4中會填滿剩餘之絕 、彖層118的材料118b。值得注意的是，形成間隙壁η% ^剩餘之絕顧118的材料mb的目的是為了填滿第一溝 =U4及後盍第二溝渠116表面的基底100材料，且間隙 曰暴路第二溝渠116底部的部分基底100。如此， - 1 = ’可以選擇性地移除間隙壁118&之間的第 二=Τ底部的部分基底100，從而加深第二溝渠116 壁118a及剩餘易之/二，只要能夠達成上述的目的，間隙 ’、之、、、巴、、彖層118的材料118b可以利用其他的 11 13 009爲备 84 19619twf.doc/g 方法來形成，而不限於以上述的步驟來形成。 接著，移除間隙壁118a之間的第二溝渠116底部的 部分基底100,以使第二溝渠116的深度D2大於第一溝竿 114的深度D1。值得-提的是，本發明是以自行對準的= 式加深第二溝渠116的深度，而不是以微影製程來定義。 由於省略了微影製程，因此本發明的隔離結構的製造方 具有製程較簡單及成本較低的優勢。 之後，明參如、圖5，移除罩幕層1 i〇a、罩幕層1⑽&、 間隙土 118a及填滿第—溝渠114的殘餘的絕緣㉟⑽ 118b。其中移除的方法例如是祕刻製程。另彳，在本告 施例中，由於必需在後續的製財以罩幕層跑來當作ς 磨、冬止層’因此上相移除步驟可以省略移除罩幕層⑽ =料。事實上，在另—實施例中，上述的移除步驟可以 省略A外’在又—實施例中，可以利賴刻選擇性， 遥擇移除罩幕層ll〇a，甘 層__心此二間二 „ , 1〇 、隹此11形中，位於第一溝渠114内的間 IT的絕緣層118材料U8b會構成隔離結構 心° ^隔__形成輕將在町詳細說明。 之、後/月參照圖6，形成一層介電層120於第一溝渠 =4及第一溝渠116中。介電層m的材質例如是氧化石夕。 』|電層12〇的形成方法例如是先形成一層絕緣材料層在基 f刪^方’以覆蓋罩幕層1〇8a，並填滿第一溝渠m及 溝渠116。然後，進行化學機械研磨製程以及回钕刻 衣程，直到暴露罩幕層1〇8a，*形成之。亦即，在本實施 12 13 00^^^584 19619twf.doc/g 13 00^^^584 19619twf.doc/g 例中罩幕層l〇8a是用於作為介電層i20的研磨終止層。在 形成隔離結構之後’移除罩幕層l〇8a及塾氧化声。 本技術領域中具有通常知識者均熟知移除罩幕層】〇如及 墊氧化層106a的方法，故於此不再贅述。如此，在第一區 域102及第二區域104的基底100中形成了具有兩種深度 的隔離結構。其中第二區域1〇4的隔離結構的深度較深， 因而具有較好的隔離能力。在另一實施例中，第二 的隔離結構更可以是一種深溝渠隔離結構，以防止後續形 成在第二區域104上的主動元件之間發生閂鎖現象。 之，第二溝渠116的深度可以超過基底1〇〇上的井區（wdf) 或磊晶層（epitaxial layer)的厚度。再者，在第二溝渠ιΐ6 内更可以形成上述介電層12〇,也可以形成其^的^電材 料、多—晶石夕、摻雜多晶石夕、金屬或鈦/氮化鈦的複合結構。 綜上所述，本發明的製造方法能夠以一次微影製程來 製造不同深度的隔離結構，以降低製程的複雜性並降低紫 ’本發明的製造方法可以整合賴渠隔離結 、版权，*而進-步防止絲元件之間的干擾或閃鎖現 =本發明已以較佳實施例揭露如上，然其並非用以 =㉝明’任何熟習此技藝者，在*脫離本發明之 内’當可作些許之更動與潤飾，因此本發明之保護 辄圍§視後附之申請專利範圍所界定者為準。 、 13 1300觸 684 19619twf.doc/g • · 【圖式簡單說明】 圖1至圖6是本發明一實施例的一種隔離結構的製造 方法剖面流程圖。 【主要元件符號說明】 100 ： 基底 102 ： 第一區域 104 ： 第二區域 106、 106a :墊氧化層 108、108a、110、110a :罩幕層 118 :絕緣層 114 :第一溝渠 116 :第二溝渠 118a :間隙壁 118b :殘餘之絕緣層的材料 120 :介電層 D1 :第一溝渠的深度 D2 :第二溝渠的深度 W1 :第一溝渠的寬度 W2 :第二溝渠的寬度 14Shixi broken glass, Shi Peng stone, stone glass or more 曰〇 ^ ^ 1 1 A For example, chemical vapor deposition = 曰 ' ' and the formation of the mask layer 110 and then 'Please refer to Figure 2 'patterned mask The layer 11 is formed to form a masking mask layer 110, for example, by using an optical micro-shadow system: a layer-forming photoresist layer on the 11G. The exposed mask layer 110 is then removed in a dry = J process. After that, remove the above 』: resist layer. The patterned photoresist layer may also be removed after the trench. Windscreen The curtain layer 11Ga is a mask, the exposed mask layer 108 is removed, and the mask layer is exposed, and the purified layer just = oxide layer (10)' is exposed to form the tantalum oxide chamber a. Wherein, in addition, the method of 9 cover: layer: 2 is, for example, a dry side course. The function of the mask layer 110a is to be used in the shape of the substrate 1 ′, so that the method is ok as long as the mask layer 11Ga can achieve this. Forming and, in another embodiment, the step of forming the tantalum oxide intestine = patterned pad oxide layer may be omitted, or other pad oxide layers 106 and 106a may be used. In addition, in the present embodiment, it is exemplified by forming two layers of material without layer lla and irrigating a, and of course, forming a single layer of mask layer on the other. 71. Subsequently, referring to FIG. 3, the substrate 100 is patterned with the mask layers 11〇& and 1〇8 to form a plurality of first 114 in the first region 1〇2, and in the second region 1 ( A plurality of second trenches 116 are formed in the 4th. Wherein g 13009 鯓 684 19619 twf.doc / g The width W1 of one trench 114 is smaller than the width W2 of the second trench. The method of patterning the substrate 100 is, for example, a dry etching process. Moreover, the present invention does not limit the method of patterning the substrate 100. For example, the substrate 1 can be patterned directly using a lithography process and a etch process without first forming the mask layers 110a and 108a. Next, a conformal insulating layer 118 is formed over the substrate 1A. This insulating layer 118 fills the first trench 114 but does not fill the second trench 116. The material of the insulating layer 118 is, for example, ruthenium oxide, and the method of forming the insulating layer 118 is, for example, a chemical vapor deposition method. Then, referring to FIG. 4, a portion of the insulating layer 118 is removed to form a spacer n8a on the sidewall of the second trench 116 that exposes the bottom of the second trench 116 of the second region 1-4. A method in which a portion of the insulating layer 118 is removed is, for example, a dry-type process. Further, in the present embodiment, the width W1 of the first trench 114 of the first region 102 is smaller than the width W2 of the first trench y4 of the second region 1〇4. Therefore, after the dry-cut process described above, the spacers 118a are formed on the sidewalls of the second region 104 of the first region 104, and the first trenches 4 of the first region 1〇2 are filled with the remaining trenches The material 118b of the layer 118. It should be noted that the purpose of forming the spacer η% ^ remaining material 118 of the desperate 118 is to fill the first trench = U4 and the back substrate of the second trench 116 surface of the substrate 100 material, and the gap 曰 blast road second A portion of the substrate 100 at the bottom of the trench 116. Thus, -1 = 'a portion of the substrate 100 at the bottom of the second = Τ between the spacers 118 & can be selectively removed, thereby deepening the second trench 116 wall 118a and the remaining easy/two, as long as the above objective can be achieved The material 118b of the gap ', 、, 、, 、, 彖 layer 118 may be formed by using other 11 13 009 as a method of 84 19619 twf.doc/g, and is not limited to being formed by the above steps. Next, a portion of the substrate 100 at the bottom of the second trench 116 between the spacers 118a is removed such that the depth D2 of the second trench 116 is greater than the depth D1 of the first trench 114. It is worth mentioning that the present invention deepens the depth of the second trench 116 by self-aligning = instead of being defined by a lithography process. Since the lithography process is omitted, the manufacturer of the isolation structure of the present invention has the advantages of relatively simple process and low cost. Thereafter, as shown in Fig. 5, the mask layer 1 i〇a, the mask layer 1 (10) & the spacer soil 118a and the residual insulation 35 (10) 118b filling the first trench 114 are removed. The method of removing is, for example, a secret engraving process. In addition, in the present embodiment, since it is necessary to run the cover layer as a honing and winter stop layer in the subsequent production, the upper phase removing step can omit the removal of the mask layer (10). In fact, in another embodiment, the above-mentioned removal step may omit A's. In addition, in the embodiment, the selective selectivity may be removed, and the mask layer ll〇a may be removed. The two U1, 1〇, and 1111 shapes, the material of the insulating layer 118 in the first trench 114, the material U8b will constitute the isolation structure of the heart, and the formation of the light will be detailed in the town. Referring to FIG. 6 , a dielectric layer 120 is formed in the first trench = 4 and the first trench 116. The material of the dielectric layer m is, for example, oxidized oxide. The method of forming the electrical layer 12 例如 is, for example, Forming a layer of insulating material at the base to cover the mask layer 1〇8a, and filling the first trench m and the trench 116. Then, performing a chemical mechanical polishing process and returning the etching process until the mask is exposed The layer 1〇8a,* is formed. That is, in the embodiment 12 13 00^^^584 19619twf.doc/g 13 00^^^584 19619twf.doc/g, the mask layer l〇8a is used as a polishing stop layer of the dielectric layer i20. After the isolation structure is formed, the mask layer l8a and the oxidized sound are removed. Those skilled in the art are familiar with the knowledge. The method of removing the mask layer, such as the pad oxide layer 106a, is not described here. Thus, an isolation structure having two depths is formed in the substrate 100 of the first region 102 and the second region 104. The isolation structure of the second region 1〇4 has a deeper depth and thus has better isolation capability. In another embodiment, the second isolation structure may be a deep trench isolation structure to prevent subsequent formation in the second region. A latch-up phenomenon occurs between the active elements on the region 104. The depth of the second trench 116 may exceed the thickness of the well region (wdf) or epitaxial layer on the substrate 1 再. The dielectric layer 12〇 can be formed in the second trench ΐ6, and a composite structure of the electro-technical material, the multi-crystall, the doped polycrystalline, the metal or the titanium/titanium nitride can be formed. According to the manufacturing method of the present invention, the isolation structure of different depths can be manufactured by one lithography process to reduce the complexity of the process and reduce the purple. The manufacturing method of the present invention can integrate the isolation and copyright of the canal, and the copyright is improved. Step prevention of wire components Interference or flash lock is now the present invention has been disclosed in the preferred embodiment as above, but it is not intended to be used by anyone skilled in the art, and within the scope of the present invention, it may be modified and retouched. Therefore, the protection scope of the present invention is defined by the scope of the appended patent application. 13, 13 1300 684 19619 twf.doc/g • · [Simple Description of the Drawings] FIGS. 1 to 6 are an embodiment of the present invention. A cross-sectional flow chart of a method for manufacturing an isolation structure. [Main element symbol description] 100: Substrate 102: First region 104: Second region 106, 106a: pad oxide layer 108, 108a, 110, 110a: mask layer 118 : Insulation layer 114: first trench 116: second trench 118a: spacer 118b: material of residual insulating layer 120: dielectric layer D1: depth D2 of the first trench: depth W1 of the second trench: first trench Width W2: width of the second trench 14