JP2004214265A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
JP2004214265A
JP2004214265A JP2002379270A JP2002379270A JP2004214265A JP 2004214265 A JP2004214265 A JP 2004214265A JP 2002379270 A JP2002379270 A JP 2002379270A JP 2002379270 A JP2002379270 A JP 2002379270A JP 2004214265 A JP2004214265 A JP 2004214265A
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Japan
Prior art keywords
electrode
layer
semiconductor device
electrode portion
semiconductor element
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Pending
Application number
JP2002379270A
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English (en)
Japanese (ja)
Inventor
Hiroshi Nakagawa
宏史 中川
Yoshihiro Kobayashi
良弘 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxell Ltd
Original Assignee
Kyushu Hitachi Maxell Ltd
Hitachi Maxell Ltd
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Application filed by Kyushu Hitachi Maxell Ltd, Hitachi Maxell Ltd filed Critical Kyushu Hitachi Maxell Ltd
Priority to JP2002379270A priority Critical patent/JP2004214265A/ja
Publication of JP2004214265A publication Critical patent/JP2004214265A/ja
Priority to JP2008268083A priority patent/JP4911727B2/ja
Priority to JP2011171781A priority patent/JP2011216921A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2002379270A 2002-12-27 2002-12-27 半導体装置および半導体装置の製造方法 Pending JP2004214265A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002379270A JP2004214265A (ja) 2002-12-27 2002-12-27 半導体装置および半導体装置の製造方法
JP2008268083A JP4911727B2 (ja) 2002-12-27 2008-10-17 半導体装置の製造方法
JP2011171781A JP2011216921A (ja) 2002-12-27 2011-08-05 半導体装置および半導体装置の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002379270A JP2004214265A (ja) 2002-12-27 2002-12-27 半導体装置および半導体装置の製造方法
JP2008268083A JP4911727B2 (ja) 2002-12-27 2008-10-17 半導体装置の製造方法
JP2011171781A JP2011216921A (ja) 2002-12-27 2011-08-05 半導体装置および半導体装置の製造方法

Related Child Applications (1)

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JP2008268083A Division JP4911727B2 (ja) 2002-12-27 2008-10-17 半導体装置の製造方法

Publications (1)

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JP2004214265A true JP2004214265A (ja) 2004-07-29

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Application Number Title Priority Date Filing Date
JP2002379270A Pending JP2004214265A (ja) 2002-12-27 2002-12-27 半導体装置および半導体装置の製造方法
JP2008268083A Expired - Lifetime JP4911727B2 (ja) 2002-12-27 2008-10-17 半導体装置の製造方法
JP2011171781A Pending JP2011216921A (ja) 2002-12-27 2011-08-05 半導体装置および半導体装置の製造方法

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JP2008268083A Expired - Lifetime JP4911727B2 (ja) 2002-12-27 2008-10-17 半導体装置の製造方法
JP2011171781A Pending JP2011216921A (ja) 2002-12-27 2011-08-05 半導体装置および半導体装置の製造方法

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Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250813A (ja) * 2006-03-16 2007-09-27 Renesas Technology Corp 半導体装置の製造方法
JP2008270265A (ja) * 2007-04-16 2008-11-06 Sumitomo Metal Mining Package Materials Co Ltd 半導体装置用基板及びその製造方法
JP2009135417A (ja) * 2007-11-07 2009-06-18 Sumitomo Metal Mining Co Ltd 半導体素子搭載用基板の製造方法
JP2009141180A (ja) * 2007-12-07 2009-06-25 Sumitomo Metal Mining Co Ltd 半導体装置製造用基板とその製造方法
JP2010040911A (ja) * 2008-08-07 2010-02-18 Renesas Technology Corp 半導体装置の製造方法
JP2010040679A (ja) * 2008-08-01 2010-02-18 Kyushu Hitachi Maxell Ltd 半導体装置とその製造方法
JP2010080656A (ja) * 2008-09-25 2010-04-08 Kyushu Hitachi Maxell Ltd 半導体装置とその製造方法
KR101006945B1 (ko) 2007-11-07 2011-01-12 스미토모 긴조쿠 고잔 가부시키가이샤 반도체 소자 탑재용 기판의 제조 방법
US7888869B2 (en) 2005-12-02 2011-02-15 Nichia Corporation Light emitting device
JP2011146524A (ja) * 2010-01-14 2011-07-28 Dainippon Printing Co Ltd リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
JP2012164862A (ja) * 2011-02-08 2012-08-30 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2012164863A (ja) * 2011-02-08 2012-08-30 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2014022582A (ja) * 2012-07-19 2014-02-03 Hitachi Maxell Ltd 半導体装置の製造方法、及び半導体装置
US8669649B2 (en) 2010-09-24 2014-03-11 Stats Chippac Ltd. Integrated circuit packaging system with interlock and method of manufacture thereof
JP2014135509A (ja) * 2014-03-19 2014-07-24 Hitachi Maxell Ltd 半導体装置用の中間成形品及び半導体装置
JP2017046014A (ja) * 2016-12-01 2017-03-02 日亜化学工業株式会社 光半導体装置
JP2017112176A (ja) * 2015-12-15 2017-06-22 Ｓｈマテリアル株式会社 半導体素子搭載用基板及び半導体装置、並びにそれらの製造方法
JP2018022821A (ja) * 2016-08-05 2018-02-08 マクセルホールディングス株式会社 半導体装置用基板およびその製造方法、半導体装置の製造方法
JP2018046311A (ja) * 2017-12-27 2018-03-22 マクセルホールディングス株式会社 半導体装置用基板の製造方法、及び半導体装置の製造方法
JP2018046310A (ja) * 2017-12-27 2018-03-22 マクセルホールディングス株式会社 半導体装置用基板、当該基板の製造方法、及び半導体装置
JP2019096901A (ja) * 2019-02-06 2019-06-20 マクセルホールディングス株式会社 半導体装置および半導体装置の製造方法
JP2021005739A (ja) * 2014-12-27 2021-01-14 マクセルホールディングス株式会社 半導体装置用基板及びその製造方法、半導体装置
JP2021082643A (ja) * 2019-11-15 2021-05-27 ローム株式会社 半導体装置の製造方法及び半導体装置
JP2021145060A (ja) * 2020-03-12 2021-09-24 マクセルホールディングス株式会社 半導体装置用基板、半導体装置用基板の製造方法および半導体装置

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JP2004214265A (ja) * 2002-12-27 2004-07-29 Kyushu Hitachi Maxell Ltd 半導体装置および半導体装置の製造方法
JP5546363B2 (ja) * 2010-06-11 2014-07-09 ローム株式会社 半導体装置および半導体装置の製造方法
JP6044936B2 (ja) 2013-04-24 2016-12-14 Ｓｈマテリアル株式会社 半導体素子搭載用基板の製造方法
JP7075571B2 (ja) * 2017-03-30 2022-05-26 マクセル株式会社 半導体装置の製造方法および半導体装置用基板
JP2019161238A (ja) * 2019-06-17 2019-09-19 マクセルホールディングス株式会社 半導体装置用基板およびその製造方法、半導体装置
JP7011685B2 (ja) * 2020-07-10 2022-01-27 マクセル株式会社 半導体装置

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Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888869B2 (en) 2005-12-02 2011-02-15 Nichia Corporation Light emitting device
JP2007250813A (ja) * 2006-03-16 2007-09-27 Renesas Technology Corp 半導体装置の製造方法
JP2008270265A (ja) * 2007-04-16 2008-11-06 Sumitomo Metal Mining Package Materials Co Ltd 半導体装置用基板及びその製造方法
JP2009135417A (ja) * 2007-11-07 2009-06-18 Sumitomo Metal Mining Co Ltd 半導体素子搭載用基板の製造方法
KR101006945B1 (ko) 2007-11-07 2011-01-12 스미토모 긴조쿠 고잔 가부시키가이샤 반도체 소자 탑재용 기판의 제조 방법
JP2009141180A (ja) * 2007-12-07 2009-06-25 Sumitomo Metal Mining Co Ltd 半導体装置製造用基板とその製造方法
JP2010040679A (ja) * 2008-08-01 2010-02-18 Kyushu Hitachi Maxell Ltd 半導体装置とその製造方法
JP2010040911A (ja) * 2008-08-07 2010-02-18 Renesas Technology Corp 半導体装置の製造方法
JP2010080656A (ja) * 2008-09-25 2010-04-08 Kyushu Hitachi Maxell Ltd 半導体装置とその製造方法
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