JP2002076040A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JP2002076040A
JP2002076040A JP2000261355A JP2000261355A JP2002076040A JP 2002076040 A JP2002076040 A JP 2002076040A JP 2000261355 A JP2000261355 A JP 2000261355A JP 2000261355 A JP2000261355 A JP 2000261355A JP 2002076040 A JP2002076040 A JP 2002076040A
Authority
JP
Japan
Prior art keywords
sealing body
resin sealing
substrate
resin
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000261355A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002076040A5 (enExample
Inventor
Tadatoshi Danno
忠敏 団野
Katsuo Arai
克夫 新井
Kazuo Shimizu
一男 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000261355A priority Critical patent/JP2002076040A/ja
Priority to US09/910,833 priority patent/US6838315B2/en
Priority to TW090118313A priority patent/TW543129B/zh
Priority to KR1020010052441A priority patent/KR100859624B1/ko
Publication of JP2002076040A publication Critical patent/JP2002076040A/ja
Publication of JP2002076040A5 publication Critical patent/JP2002076040A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2000261355A 2000-08-30 2000-08-30 半導体装置及びその製造方法 Pending JP2002076040A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000261355A JP2002076040A (ja) 2000-08-30 2000-08-30 半導体装置及びその製造方法
US09/910,833 US6838315B2 (en) 2000-08-30 2001-07-24 Semiconductor device manufacturing method wherein electrode members are exposed from a mounting surface of a resin encapsulator
TW090118313A TW543129B (en) 2000-08-30 2001-07-26 A semiconductor device and a method of manufacturing the same
KR1020010052441A KR100859624B1 (ko) 2000-08-30 2001-08-29 반도체 장치의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000261355A JP2002076040A (ja) 2000-08-30 2000-08-30 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2002076040A true JP2002076040A (ja) 2002-03-15
JP2002076040A5 JP2002076040A5 (enExample) 2005-03-17

Family

ID=18749210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000261355A Pending JP2002076040A (ja) 2000-08-30 2000-08-30 半導体装置及びその製造方法

Country Status (4)

Country Link
US (1) US6838315B2 (enExample)
JP (1) JP2002076040A (enExample)
KR (1) KR100859624B1 (enExample)
TW (1) TW543129B (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7335529B2 (en) 2002-04-10 2008-02-26 Renesas Technology Corp. Manufacturing method of a semiconductor device utilizing a flexible adhesive tape
JPWO2006009030A1 (ja) * 2004-07-15 2008-05-01 大日本印刷株式会社 半導体装置及び半導体装置製造用基板並びにそれらの製造方法
JP2009516373A (ja) * 2005-11-14 2009-04-16 アナログ デバイシーズ インク 露出型ダイパッケージの製造方法
JP2009123873A (ja) * 2007-11-14 2009-06-04 Wen-Gung Sung 発光ダイオード封止構造およびその製造方法
JP2009530870A (ja) * 2006-03-20 2009-08-27 マイクロン テクノロジー， インク． 集積回路デバイスのためのキャリアレスチップパッケージ、および、それを作成する方法
JP2013038214A (ja) * 2011-08-08 2013-02-21 Renesas Electronics Corp 半導体装置の製造方法
JP2015213151A (ja) * 2014-04-16 2015-11-26 株式会社村田製作所 半導体パッケージおよびこれを備える半導体モジュール
JP2018032852A (ja) * 2016-08-22 2018-03-01 ローム株式会社 半導体装置、半導体装置の実装構造

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US7026710B2 (en) * 2000-01-21 2006-04-11 Texas Instruments Incorporated Molded package for micromechanical devices and method of fabrication
JP2002118201A (ja) * 2000-10-05 2002-04-19 Hitachi Ltd 半導体装置およびその製造方法
JP3973457B2 (ja) * 2002-03-15 2007-09-12 シャープ株式会社 半導体発光装置
US6921975B2 (en) * 2003-04-18 2005-07-26 Freescale Semiconductor, Inc. Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
DE10334576B4 (de) * 2003-07-28 2007-04-05 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse
JP2006073586A (ja) * 2004-08-31 2006-03-16 Renesas Technology Corp 半導体装置の製造方法
CN101310379B (zh) * 2005-11-17 2010-09-15 富士通半导体股份有限公司 半导体器件
JP2008016630A (ja) * 2006-07-06 2008-01-24 Matsushita Electric Ind Co Ltd プリント配線板およびその製造方法
CN101101882A (zh) * 2006-07-05 2008-01-09 阎跃军 基板树脂封装方法
CN100505246C (zh) * 2006-09-30 2009-06-24 卓恩民 半导体封装结构及其制法
DE102007034402B4 (de) * 2006-12-14 2014-06-18 Advanpack Solutions Pte. Ltd. Halbleiterpackung und Herstellungsverfahren dafür
KR100874923B1 (ko) * 2007-04-02 2008-12-19 삼성전자주식회사 멀티 스택 패키지, 이의 제조 방법 및 이를 제조하기 위한반도체 패키지 금형
JP2012506156A (ja) * 2008-10-17 2012-03-08 オッカム ポートフォリオ リミテッド ライアビリティ カンパニー はんだを使用しないフレキシブル回路アセンブリおよび製造方法
TWI414048B (zh) * 2008-11-07 2013-11-01 先進封裝技術私人有限公司 半導體封裝件與其製造方法
TWI381496B (zh) 2009-01-23 2013-01-01 億光電子工業股份有限公司 封裝基板結構與晶片封裝結構及其製程
US20120241926A1 (en) * 2011-03-23 2012-09-27 Zigmund Ramirez Camacho Integrated circuit packaging system with leveling standoff and method of manufacture thereof
US8420448B2 (en) * 2011-03-24 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with pads and method of manufacture thereof
US9301391B2 (en) 2011-11-29 2016-03-29 Advanpack Solutions Pte Ltd. Substrate structure, semiconductor package device, and manufacturing method of substrate structure
TWI476841B (zh) * 2012-03-03 2015-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP5919087B2 (ja) * 2012-05-10 2016-05-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
TWI488275B (zh) * 2013-05-20 2015-06-11 矽品精密工業股份有限公司 半導體封裝件之製法
DE102014103942B4 (de) * 2014-03-21 2024-05-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Gehäuses für ein elektronisches Bauelement und eines elektronischen Bauelements, Gehäuse für ein elektronisches Bauelement und elektronisches Bauelement
JP6612723B2 (ja) * 2016-12-07 2019-11-27 株式会社東芝 基板装置
US9978613B1 (en) 2017-03-07 2018-05-22 Texas Instruments Incorporated Method for making lead frames for integrated circuit packages
US20250293221A1 (en) * 2024-03-14 2025-09-18 Advanced Semiconductor Engineering, Inc. Electronic device

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JP2781020B2 (ja) * 1989-09-06 1998-07-30 モトローラ・インコーポレーテッド 半導体装置およびその製造方法
JP2781019B2 (ja) * 1989-09-06 1998-07-30 新光電気工業株式会社 半導体装置およびその製造方法
US5435482A (en) * 1994-02-04 1995-07-25 Lsi Logic Corporation Integrated circuit having a coplanar solder ball contact array
US5972736A (en) * 1994-12-21 1999-10-26 Sun Microsystems, Inc. Integrated circuit package and method
US5661086A (en) * 1995-03-28 1997-08-26 Mitsui High-Tec, Inc. Process for manufacturing a plurality of strip lead frame semiconductor devices
JP3170199B2 (ja) * 1996-03-15 2001-05-28 株式会社東芝 半導体装置及びその製造方法及び基板フレーム
US5989939A (en) * 1996-12-13 1999-11-23 Tessera, Inc. Process of manufacturing compliant wirebond packages
JP3032964B2 (ja) * 1996-12-30 2000-04-17 アナムインダストリアル株式会社 ボールグリッドアレイ半導体のパッケージ及び製造方法
US6365438B1 (en) * 1997-05-09 2002-04-02 Citizen Watch Co., Ltd. Process for manufacturing semiconductor package and circuit board assembly
JP2954148B1 (ja) 1998-03-25 1999-09-27 松下電子工業株式会社 樹脂封止型半導体装置の製造方法およびその製造装置
US6235387B1 (en) * 1998-03-30 2001-05-22 3M Innovative Properties Company Semiconductor wafer processing tapes
JP3424184B2 (ja) 1998-05-13 2003-07-07 株式会社三井ハイテック 樹脂封止型半導体装置
US6117797A (en) * 1998-09-03 2000-09-12 Micron Technology, Inc. Attachment method for heat sinks and devices involving removal of misplaced encapsulant
TW428295B (en) * 1999-02-24 2001-04-01 Matsushita Electronics Corp Resin-sealing semiconductor device, the manufacturing method and the lead frame thereof
US6291884B1 (en) * 1999-11-09 2001-09-18 Amkor Technology, Inc. Chip-size semiconductor packages
US6404648B1 (en) * 2001-03-30 2002-06-11 Hewlett-Packard Co. Assembly and method for constructing a multi-die integrated circuit

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7335529B2 (en) 2002-04-10 2008-02-26 Renesas Technology Corp. Manufacturing method of a semiconductor device utilizing a flexible adhesive tape
JPWO2006009030A1 (ja) * 2004-07-15 2008-05-01 大日本印刷株式会社 半導体装置及び半導体装置製造用基板並びにそれらの製造方法
JP4842812B2 (ja) * 2004-07-15 2011-12-21 大日本印刷株式会社 半導体装置用基板の製造方法
JP2009516373A (ja) * 2005-11-14 2009-04-16 アナログ デバイシーズ インク 露出型ダイパッケージの製造方法
JP2009530870A (ja) * 2006-03-20 2009-08-27 マイクロン テクノロジー， インク． 集積回路デバイスのためのキャリアレスチップパッケージ、および、それを作成する方法
JP2009123873A (ja) * 2007-11-14 2009-06-04 Wen-Gung Sung 発光ダイオード封止構造およびその製造方法
JP2013038214A (ja) * 2011-08-08 2013-02-21 Renesas Electronics Corp 半導体装置の製造方法
US8513060B2 (en) 2011-08-08 2013-08-20 Renesas Electronics Corporation Manufacturing method using multi-step adhesive curing for sealed semiconductor device
JP2015213151A (ja) * 2014-04-16 2015-11-26 株式会社村田製作所 半導体パッケージおよびこれを備える半導体モジュール
JP2018032852A (ja) * 2016-08-22 2018-03-01 ローム株式会社 半導体装置、半導体装置の実装構造

Also Published As

Publication number Publication date
KR20020018103A (ko) 2002-03-07
US20020025607A1 (en) 2002-02-28
US6838315B2 (en) 2005-01-04
TW543129B (en) 2003-07-21
KR100859624B1 (ko) 2008-09-23

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