JP2001203263A - 半導体集積回路装置の製造方法および半導体集積回路装置 - Google Patents
半導体集積回路装置の製造方法および半導体集積回路装置Info
- Publication number
- JP2001203263A JP2001203263A JP2000012026A JP2000012026A JP2001203263A JP 2001203263 A JP2001203263 A JP 2001203263A JP 2000012026 A JP2000012026 A JP 2000012026A JP 2000012026 A JP2000012026 A JP 2000012026A JP 2001203263 A JP2001203263 A JP 2001203263A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- integrated circuit
- circuit device
- semiconductor integrated
- separation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
- H10D89/105—Integrated device layouts adapted for thermal considerations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Priority Applications (11)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000012026A JP2001203263A (ja) | 2000-01-20 | 2000-01-20 | 半導体集積回路装置の製造方法および半導体集積回路装置 |
| US09/709,403 US6693008B1 (en) | 2000-01-20 | 2000-11-13 | Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device |
| TW089128142A TW477061B (en) | 2000-01-20 | 2000-12-28 | Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device |
| KR1020010003154A KR100716075B1 (ko) | 2000-01-20 | 2001-01-19 | 반도체 집적 회로 장치의 제조 방법 |
| US10/721,230 US20040106292A1 (en) | 2000-01-20 | 2003-11-26 | Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device |
| US11/055,745 US7060589B2 (en) | 2000-01-20 | 2005-02-11 | Method for manufacturing a semiconductor integrated circuit device that includes covering the bottom of an isolation trench with spin-on glass and etching back the spin-on glass to a predetermined depth |
| US11/149,539 US7074691B2 (en) | 2000-01-20 | 2005-06-10 | Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material |
| US11/149,538 US7208391B2 (en) | 2000-01-20 | 2005-06-10 | Method of manufacturing a semiconductor integrated circuit device that includes forming an isolation trench around active regions and filling the trench with two insulating films |
| KR1020060080350A KR100719429B1 (ko) | 2000-01-20 | 2006-08-24 | 반도체 집적 회로 장치의 제조 방법 |
| KR1020060080347A KR100719015B1 (ko) | 2000-01-20 | 2006-08-24 | 반도체 집적 회로 장치의 제조 방법 |
| US11/653,321 US20070114631A1 (en) | 2000-01-20 | 2007-01-16 | Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000012026A JP2001203263A (ja) | 2000-01-20 | 2000-01-20 | 半導体集積回路装置の製造方法および半導体集積回路装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001203263A true JP2001203263A (ja) | 2001-07-27 |
| JP2001203263A5 JP2001203263A5 (https=) | 2007-03-08 |
Family
ID=18539805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000012026A Pending JP2001203263A (ja) | 2000-01-20 | 2000-01-20 | 半導体集積回路装置の製造方法および半導体集積回路装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (5) | US6693008B1 (https=) |
| JP (1) | JP2001203263A (https=) |
| KR (3) | KR100716075B1 (https=) |
| TW (1) | TW477061B (https=) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196843A (ja) * | 2005-01-17 | 2006-07-27 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP2006286720A (ja) * | 2005-03-31 | 2006-10-19 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP2006351694A (ja) * | 2005-06-14 | 2006-12-28 | Fujitsu Ltd | 半導体装置およびその製造方法 |
| JP2007335807A (ja) * | 2006-06-19 | 2007-12-27 | Toshiba Corp | 半導体装置の製造方法 |
| JP2008124517A (ja) * | 2008-02-15 | 2008-05-29 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
| US7416987B2 (en) | 2003-11-28 | 2008-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| US7948038B2 (en) | 2004-05-18 | 2011-05-24 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and process of manufacturing the same |
| US8384187B2 (en) | 2009-05-08 | 2013-02-26 | Renesas Electronics Corporation | Semiconductor device with shallow trench isolation |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004096065A (ja) * | 2002-07-08 | 2004-03-25 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
| DE10261807A1 (de) | 2002-12-19 | 2004-07-01 | Turicum Drug Development Ag | Deuterierte Catecholaminderivate sowie diese Verbindungen enthaltende Arzneimittel |
| US7214595B2 (en) * | 2003-06-27 | 2007-05-08 | Kabushiki Kaisha Toshiba | Method of producing semiconductor devices |
| US7037840B2 (en) * | 2004-01-26 | 2006-05-02 | Micron Technology, Inc. | Methods of forming planarized surfaces over semiconductor substrates |
| JP4955222B2 (ja) | 2005-05-20 | 2012-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US7811935B2 (en) * | 2006-03-07 | 2010-10-12 | Micron Technology, Inc. | Isolation regions and their formation |
| KR100816749B1 (ko) * | 2006-07-12 | 2008-03-27 | 삼성전자주식회사 | 소자분리막, 상기 소자분리막을 구비하는 비휘발성 메모리소자, 그리고 상기 소자분리막 및 비휘발성 메모리 소자형성 방법들 |
| US7696057B2 (en) * | 2007-01-02 | 2010-04-13 | International Business Machines Corporation | Method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
| US8129816B2 (en) * | 2007-06-20 | 2012-03-06 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US20090004839A1 (en) * | 2007-06-28 | 2009-01-01 | Hynix Semiconductor Inc. | Method for fabricating an interlayer dielectric in a semiconductor device |
| WO2009079460A1 (en) * | 2007-12-14 | 2009-06-25 | University Of Florida Research Foundation, Inc. | Electrothermal microactuator for large vertical displacement without tilt or lateral shift |
| TWI396259B (zh) * | 2009-08-28 | 2013-05-11 | 華亞科技股份有限公司 | 動態隨機存取記憶體之凹溝渠通道之自我對準方法 |
| US9013915B2 (en) * | 2010-03-30 | 2015-04-21 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| KR101177996B1 (ko) * | 2010-10-15 | 2012-08-28 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
| JP5859758B2 (ja) * | 2011-07-05 | 2016-02-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US9121237B2 (en) | 2011-07-28 | 2015-09-01 | Baker Hughes Incorporated | Methods of coating wellbore tools and components having such coatings |
| US8697537B2 (en) * | 2012-02-01 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of patterning for a semiconductor device |
| US8603895B1 (en) * | 2012-09-11 | 2013-12-10 | Globalfoundries Inc. | Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence |
| US10204794B2 (en) | 2013-12-23 | 2019-02-12 | Intel Corporation | Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures |
| US9559184B2 (en) | 2015-06-15 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices including gate spacer with gap or void and methods of forming the same |
| KR102404642B1 (ko) * | 2015-07-17 | 2022-06-03 | 삼성전자주식회사 | 반도체 소자 및 이의 제조방법 |
| US9847245B1 (en) * | 2016-06-16 | 2017-12-19 | Samsung Electronics Co., Ltd. | Filling processes |
| CN108281354B (zh) * | 2017-01-06 | 2022-07-12 | 联华电子股份有限公司 | 平坦化方法 |
| CN109390338B (zh) * | 2017-08-08 | 2021-06-22 | 联华电子股份有限公司 | 互补式金属氧化物半导体元件及其制作方法 |
| CN109817521B (zh) * | 2017-11-21 | 2022-04-12 | 联华电子股份有限公司 | 用来改善平坦化负载效应的半导体制作工艺 |
| JP2022094651A (ja) * | 2020-12-15 | 2022-06-27 | キオクシア株式会社 | 半導体装置および半導体装置の製造方法 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020530A (ja) * | 1983-07-14 | 1985-02-01 | Nec Corp | 素子分離領域の形成方法 |
| JPS62133733A (ja) * | 1985-12-05 | 1987-06-16 | Nec Corp | 半導体集積回路装置 |
| JPS62173738A (ja) * | 1986-01-22 | 1987-07-30 | シ−メンス、アクチエンゲゼルシヤフト | 集積半導体回路の絶縁分離溝の充填方法 |
| JPH10209266A (ja) * | 1997-01-27 | 1998-08-07 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| JP2000114362A (ja) * | 1998-10-02 | 2000-04-21 | Nec Corp | 半導体装置の製造方法 |
| JP2000183150A (ja) * | 1998-12-11 | 2000-06-30 | Matsushita Electronics Industry Corp | 半導体装置の製造方法 |
Family Cites Families (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US182798A (en) * | 1876-10-03 | Improvement in machines for winding spiral studs | ||
| US4994231A (en) | 1990-03-22 | 1991-02-19 | The Babcock & Wilcox Company | Apparatus for blending constituents of varying densities |
| US5098856A (en) * | 1991-06-18 | 1992-03-24 | International Business Machines Corporation | Air-filled isolation trench with chemically vapor deposited silicon dioxide cap |
| JPH05114646A (ja) | 1991-10-24 | 1993-05-07 | Fujitsu Ltd | 半導体装置の製造方法 |
| US5270264A (en) * | 1991-12-20 | 1993-12-14 | Intel Corporation | Process for filling submicron spaces with dielectric |
| JPH05235157A (ja) | 1992-02-26 | 1993-09-10 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH064776A (ja) | 1992-06-19 | 1994-01-14 | Omron Corp | 電子式キャッシュレジスタ |
| KR950009888B1 (ko) | 1992-08-14 | 1995-09-01 | 삼성전자 주식회사 | 반도체장치의 제조방법 |
| US5292689A (en) | 1992-09-04 | 1994-03-08 | International Business Machines Corporation | Method for planarizing semiconductor structure using subminimum features |
| JPH07326659A (ja) | 1994-06-02 | 1995-12-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| JP2671828B2 (ja) | 1994-10-28 | 1997-11-05 | 日本電気株式会社 | 半導体装置の製造方法 |
| JPH08148559A (ja) * | 1994-11-15 | 1996-06-07 | Fujitsu Ltd | 絶縁膜を有する半導体装置の製造方法 |
| US5960300A (en) * | 1994-12-20 | 1999-09-28 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device |
| KR0155874B1 (ko) * | 1995-08-31 | 1998-12-01 | 김광호 | 반도체장치의 평탄화방법 및 이를 이용한 소자분리방법 |
| KR0165462B1 (ko) * | 1995-10-28 | 1999-02-01 | 김광호 | 트렌치 소자 분리 방법 |
| US5827782A (en) * | 1996-06-03 | 1998-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple etch method for optimizing Inter-Metal Dielectric (IMD) spacer layer profile |
| US6060352A (en) * | 1996-08-09 | 2000-05-09 | Hitachi, Ltd. | Method of manufacturing semiconductor device with increased focus margin |
| EP0851463A1 (en) | 1996-12-24 | 1998-07-01 | STMicroelectronics S.r.l. | Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices |
| US5854125A (en) * | 1997-02-24 | 1998-12-29 | Vlsi Technology, Inc. | Dummy fill patterns to improve interconnect planarity |
| JP3638778B2 (ja) * | 1997-03-31 | 2005-04-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
| TW454339B (en) * | 1997-06-20 | 2001-09-11 | Hitachi Ltd | Semiconductor integrated circuit apparatus and its fabricating method |
| JP3519579B2 (ja) * | 1997-09-09 | 2004-04-19 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
| JP3309783B2 (ja) * | 1997-10-31 | 2002-07-29 | 日本電気株式会社 | 半導体装置の製造方法 |
| JP3718034B2 (ja) | 1997-11-11 | 2005-11-16 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
| JP3697044B2 (ja) * | 1997-12-19 | 2005-09-21 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
| JP3686248B2 (ja) * | 1998-01-26 | 2005-08-24 | 株式会社日立製作所 | 半導体集積回路装置およびその製造方法 |
| US6111086A (en) * | 1998-02-27 | 2000-08-29 | Scaringe; Stephen A. | Orthoester protecting groups |
| JP3718058B2 (ja) * | 1998-06-17 | 2005-11-16 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
| KR100319185B1 (ko) * | 1998-07-31 | 2002-01-04 | 윤종용 | 반도체 장치의 절연막 형성 방법 |
| TW408432B (en) * | 1998-08-25 | 2000-10-11 | United Microelectronics Corp | The manufacture method of shallow trench isolation |
| JP2000156480A (ja) | 1998-09-03 | 2000-06-06 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| TW469643B (en) * | 1998-09-04 | 2001-12-21 | Canon Kk | Process for producing semiconductor substrate |
| US6133105A (en) * | 1999-04-27 | 2000-10-17 | United Microelectronics Corp. | Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure |
| US6255649B1 (en) * | 1999-07-29 | 2001-07-03 | Xerox Corporation | Charging device with grid tensioning shafts |
-
2000
- 2000-01-20 JP JP2000012026A patent/JP2001203263A/ja active Pending
- 2000-11-13 US US09/709,403 patent/US6693008B1/en not_active Expired - Lifetime
- 2000-12-28 TW TW089128142A patent/TW477061B/zh not_active IP Right Cessation
-
2001
- 2001-01-19 KR KR1020010003154A patent/KR100716075B1/ko not_active Expired - Fee Related
-
2003
- 2003-11-26 US US10/721,230 patent/US20040106292A1/en not_active Abandoned
-
2005
- 2005-02-11 US US11/055,745 patent/US7060589B2/en not_active Expired - Fee Related
- 2005-06-10 US US11/149,538 patent/US7208391B2/en not_active Expired - Fee Related
- 2005-06-10 US US11/149,539 patent/US7074691B2/en not_active Expired - Fee Related
-
2006
- 2006-08-24 KR KR1020060080347A patent/KR100719015B1/ko not_active Expired - Fee Related
- 2006-08-24 KR KR1020060080350A patent/KR100719429B1/ko not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020530A (ja) * | 1983-07-14 | 1985-02-01 | Nec Corp | 素子分離領域の形成方法 |
| JPS62133733A (ja) * | 1985-12-05 | 1987-06-16 | Nec Corp | 半導体集積回路装置 |
| JPS62173738A (ja) * | 1986-01-22 | 1987-07-30 | シ−メンス、アクチエンゲゼルシヤフト | 集積半導体回路の絶縁分離溝の充填方法 |
| JPH10209266A (ja) * | 1997-01-27 | 1998-08-07 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| JP2000114362A (ja) * | 1998-10-02 | 2000-04-21 | Nec Corp | 半導体装置の製造方法 |
| JP2000183150A (ja) * | 1998-12-11 | 2000-06-30 | Matsushita Electronics Industry Corp | 半導体装置の製造方法 |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7416987B2 (en) | 2003-11-28 | 2008-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| US7948038B2 (en) | 2004-05-18 | 2011-05-24 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and process of manufacturing the same |
| US8217468B2 (en) | 2004-05-18 | 2012-07-10 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and process of manufacturing the same |
| US8536657B2 (en) | 2004-05-18 | 2013-09-17 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and process of manufacturing the same |
| US8679916B2 (en) | 2004-05-18 | 2014-03-25 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and process of manufacturing the same |
| JP2006196843A (ja) * | 2005-01-17 | 2006-07-27 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP2006286720A (ja) * | 2005-03-31 | 2006-10-19 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP2006351694A (ja) * | 2005-06-14 | 2006-12-28 | Fujitsu Ltd | 半導体装置およびその製造方法 |
| JP2007335807A (ja) * | 2006-06-19 | 2007-12-27 | Toshiba Corp | 半導体装置の製造方法 |
| JP2008124517A (ja) * | 2008-02-15 | 2008-05-29 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
| US8384187B2 (en) | 2009-05-08 | 2013-02-26 | Renesas Electronics Corporation | Semiconductor device with shallow trench isolation |
| US9029237B2 (en) | 2009-05-08 | 2015-05-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060097096A (ko) | 2006-09-13 |
| US7074691B2 (en) | 2006-07-11 |
| US20050237603A1 (en) | 2005-10-27 |
| KR20060096975A (ko) | 2006-09-13 |
| US20040106292A1 (en) | 2004-06-03 |
| US20050239257A1 (en) | 2005-10-27 |
| KR100719015B1 (ko) | 2007-05-16 |
| US20050148155A1 (en) | 2005-07-07 |
| TW477061B (en) | 2002-02-21 |
| KR100716075B1 (ko) | 2007-05-08 |
| KR100719429B1 (ko) | 2007-05-18 |
| US6693008B1 (en) | 2004-02-17 |
| US7208391B2 (en) | 2007-04-24 |
| KR20010076387A (ko) | 2001-08-11 |
| US7060589B2 (en) | 2006-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001203263A (ja) | 半導体集積回路装置の製造方法および半導体集積回路装置 | |
| JP4167727B2 (ja) | 半導体記憶装置 | |
| JP3445495B2 (ja) | 半導体装置 | |
| JP4074451B2 (ja) | 半導体装置の製造方法 | |
| JP5717943B2 (ja) | 半導体装置およびその製造方法 | |
| JP2001339054A (ja) | 半導体装置及びその製造方法 | |
| JP3943294B2 (ja) | 半導体集積回路装置 | |
| US20030082900A1 (en) | Method of forming contact plugs | |
| JP2005019988A (ja) | 半導体装置及びその製造方法 | |
| US20070114631A1 (en) | Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device | |
| JP2004040095A (ja) | Dramセルおよびその形成方法 | |
| US20140030865A1 (en) | Method of manufacturing semiconductor device having cylindrical lower capacitor electrode | |
| US6812092B2 (en) | Method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line contacts | |
| JP2009182114A (ja) | 半導体装置およびその製造方法 | |
| WO2014125950A1 (ja) | 半導体装置及びその製造方法 | |
| US20100181623A1 (en) | Semiconductor device having dummy bit line structure | |
| JP2004128239A (ja) | スタティック型半導体記憶装置 | |
| US6903022B2 (en) | Method of forming contact hole | |
| JP4336477B2 (ja) | 半導体集積回路装置の製造方法 | |
| US20040201043A1 (en) | Bit line contact hole and method for forming the same | |
| JP4214162B2 (ja) | 半導体記憶装置およびその製造方法 | |
| KR100528765B1 (ko) | 반도체 소자의 제조 방법 | |
| KR20070045570A (ko) | 공유 콘택 구조를 가지는 반도체 소자 및 그 제조 방법 | |
| JP2006060056A (ja) | 半導体記憶装置の製造方法および当該半導体記憶装置 | |
| JPWO2000025355A1 (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20050315 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070119 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070119 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100414 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100528 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100622 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100803 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20110607 |