CN108281354B - 平坦化方法 - Google Patents

平坦化方法 Download PDF

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CN108281354B
CN108281354B CN201710011311.1A CN201710011311A CN108281354B CN 108281354 B CN108281354 B CN 108281354B CN 201710011311 A CN201710011311 A CN 201710011311A CN 108281354 B CN108281354 B CN 108281354B
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layer
dielectric layer
stop layer
top surface
insulating layer
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CN108281354A (zh
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黄柏诚
李昱廷
蔡傅守
林文钦
刘俊良
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种平坦化方法，包含提供一基底，具有一主表面。一凸起结构，位于主表面上。形成一绝缘层，共型地覆盖主表面以及凸起结构的顶面及侧壁。形成一停止层，位于绝缘层上并且至少覆盖凸起结构的顶面。然后全面性地形成一第一介电层，并以一化学机械研磨制作工艺移除部分第一介电层直到暴露出停止层，得到一上表面。形成一预定厚度的第二介电层，覆盖上表面。

Description

平坦化方法
技术领域
本发明涉及半导体制作工艺领域，特别涉及一种平坦化方法。
背景技术
动态随机存取存储器(dynamic random access memory,DRAM)属于一种挥发性存储器，包含由多个存储单元(memory cell)构成的阵列区(array area) 以及控制电路所在的周边区(peripheral area)。一般而言，各存储单元是由一晶体管(transistor)连接一电容器(capacitor)的结构(1T1C)，通过电容存储电荷来达到存储数据的目的。
随着制成世代的演进，为了缩小存储单元的尺寸而制作出具备更高集密度的芯片，存储器的结构已朝向三维(three-dimensional)发展，例如采用冠式电容结构(crown-type capacitor)，其存储单元的电容是以垂直的方向设置在晶体管上，不仅可大幅减少电容占据的平面面积，制作上也更具弹性，例如可简单通过增加电容的高度来增加电容的电极的接触面积而得到更大的电容量。
然而，冠式电容结构(crown-type capacitor)使得存储器的阵列区和周边区之间具有明显的阶梯差(step height)，造成后续平坦化制作工艺的控制更加困难。因此，本领域仍须要一种改良的平坦化制作工艺，可克服明显的阶梯差而得到一平坦的上表面。
发明内容
本发明目的在于提供一种改良的平坦化方法，可较准确控制而制作出理想的平坦上表面。
本发明第一方面提供的平坦化方法，包含下列步骤。首先，提供一基底，具有一主表面，以及一凸起结构，位于该主表面上。接着，形成一绝缘层，共型地覆盖该主表面以及该凸起结构的顶面及侧壁，以及一停止层，位于该绝缘层上并且至少覆盖该凸起结构的顶面。然后，全面性地形成一第一介电层，并进行一化学机械研磨制作工艺，移除部分该第一介电层直到暴露出覆盖该凸起结构的顶面的该停止层，得到一包含该停止层以及该第一介电层的平坦的上表面。后续，形成一预定厚度的第二介电层，覆盖该上表面。
本发明第二方面提供的平坦化方法，包含下列步骤。首先，提供一基底，具有一主表面，以及一凸起结构，位于该主表面上。接着，形成一预定厚度的绝缘层，共型地覆盖该主表面以及该凸起结构的顶面及侧壁，以及一停止层，位于该绝缘层上并且仅覆盖该凸起结构的顶面。然后，全面性地形成一第一介电层，并进行一化学机械研磨制作工艺，移除部分该第一介电层直到暴露出覆盖该凸起结构的顶面的该停止层，得到一包含该停止层以及该第一介电层的平坦的上表面。后续，移除该停止层，暴露出覆盖该凸起结构顶面的该绝缘层。
附图说明
图1至图7为本发明第一实施例的步骤剖面示意图，其中图7为图6所示步骤的一变化型；
图8至图14为本发明第二实施例的步骤剖面示意图，其中图14为图13 所示步骤的一变化型；
图15至图20为本发明第三实施例的步骤剖面示意图。
主要元件符号说明
10 基底
10a 主表面
12 凸起结构
12a 顶面
12b 侧壁
14 盖层
16 绝缘层
18 停止层
20 光致抗蚀剂层
22 第一介电层
24 化学机械研磨制作
工艺
26 上表面
28 选择性蚀刻
29 非选择性蚀刻
30 第二介电层
H、H’ 阶梯差
A 阵列区
B 周边区
具体实施方式
图1至图7为本发明第一实施例的步骤示意图。
首先，请参考图1，提供基底10，具有主表面10a。基底10区分成阵列区A以及周边区B，其中阵列区A占了主表面10a较大的区域，例如主表面10a面积的50％以上，甚至75％以上，而周边区B占了主表面10a其余较小的区域，例如主表面10a面积的50％以下，甚至25％以下。凸起结构12 位于主表面10a上，位于阵列区A的正上方并且完全覆盖阵列区A。从顶视图来看，凸起结构12顶面12a的面积与阵列区A的面积大致相同，换句话说，是主表面10a面积的50％以上，甚至75％以上。根据本发明一实施例，基底10是一动态随机存取存储器的基底，包含多个晶体管(图未示)以及多条交错的字符线(word-line,WL)和位线(bit-line,BL)形成其中。凸起结构12是由堆叠在阵列区A正上方的冠式电容所构成，其厚度(或高度)大约是1.5至 2微米，或者，可根据电容量的需求而具有更高的厚度，因此造成阵列区A 和周边区B之间明显的阶梯差。应可理解的是，本发明也应用于其他具有明显阶梯差的元件的平坦化，并不限于实施例所述的存储器。
接着，依序形成一绝缘层16，以及一停止层18，共型地覆盖主表面10a 以及凸起结构12的顶面12a及侧壁12b。绝缘层16的厚度可小于或等于100 埃，较佳介于50埃至100埃之间，材质可包含氧化硅。但不限于此。停止层18的厚度小于或等于100埃，较佳介于50埃至100埃之间，材质可包含氮化硅(SiN)、氮氧化硅(SiON)或碳氮化硅(SiCN)，但不限于此。根据本发明一实施例，形成绝缘层16以及停止层18之前，可包含形成一盖层14，覆盖凸起结构12的顶面12a和侧壁12b并延伸至邻近凸起结构12周围的部分主表面10a。形成盖层14的方法包含先全面性地沉积盖层14，再进行一图案化制作工艺以移除部分盖层。根据本发明一实施例，盖层14可包含绝缘层，例如USG，用以保护或隔离突起结构12的电容，或包含导电层，例如钨，用来与电容结构电连接。停止层18与盖层14被绝缘层16区隔开，并不直接接触。
请参考图2和图3。接着，进行一图案化制作工艺以移除部分停止层18，步骤包含于停止层18上形成一掩模层，例如光致抗蚀剂层20，仅覆盖凸起结构12的顶面12a，暴露出位于侧壁12b和主表面10a上部分的停止层18，然后以光致抗蚀剂层20为蚀刻掩模进行蚀刻制作工艺，例如对绝缘层16和停止层18具有高选择性的蚀刻制作工艺，移除暴露的停止层18。如图所示，剩余的停止层18仅覆盖凸起结构12的顶面12a。须注意的是，绝缘层16 并不会被蚀刻移除，仍完全覆盖住凸起结构12的顶面12a、侧壁12b和基底 10的主表面10a。
请参考图4。接着，全面性地形成一第一介电层22，例如氧化硅，厚度至少大于凸起结构12的厚度，较佳约是凸起结构12厚度的两倍，以提供后续化学机械研磨制作工艺24足够的研磨厚度。由于绝缘层16的关系，第一介电层22并不会与凸起结构12和基底10直接接触。凸起结构12的厚度造成第一介电层22在阵列区A和周边区B之间具有一明显的阶梯差H。
请参考图5。接着，进行化学机械研磨制作工艺24，并利用停止层18 当作化学机械研磨制作工艺24的停止层，用以移除部分第一介电层22，直到暴露出停止层18。化学机械研磨制作工艺24的研磨液对于停止层18和第一介电层22具有高蚀刻选择比，较佳者，选择比约为1:10，即停止层18于化学机械研磨制作工艺24中的移除率小于第一介电层22于化学机械研磨制作工艺24中的移除率的十分之一。值得注意的是，如前所述，凸起结构12 占基底10总面积的大部分(大于50％，甚至大于75％)，也就是说，当研磨至停止层18暴露出来时，其面积占了研磨表面的大部分(大于50％，甚至大于75％)，因此可较有效控化学机械研磨制作工艺24的停止时间点，确保不同批的研磨量相等，另外，停止层18直接位于凸起结构12上还可达到保护凸起结构12不会被研磨而受损。如图所示，在化学机械研磨制作工艺24后，可得到一平坦的上表面26。
请参考图6和图7。后续，如图6所示，可进行一选择性蚀刻制作工艺 28，例如对于第一介电层22和停止层18具有高选择性的湿蚀刻制作工艺，移除暴露的停止层18，再全面性地形成一预定厚度的第二介电层30，例如为厚度为2500埃至3000埃之间的氧化硅层，完全覆盖阵列区A和周边区B。可选择性地对第二介电层30进行一缓冲研磨制作工艺(bufferCMP)。或者，如图7所示，可进行一非选择性蚀刻制作工艺29，例如干蚀刻制作工艺或非选择性研磨制作工艺，移除暴露的停止层18以及等量的第一介电层22，然后再全面性地形成预定厚度的第二介电层30。制作工艺至此，凸起结构12 顶面12a是仅由绝缘层16和第二介电层30覆盖，以提供隔离与保护的功能。
图8至图14为本发明第二实施例的步骤示意图，其中各结构的材质与第一实施例相同，为了简化而与图1至图7使用相同的附图标记。与第一实施例的差异处在于，第二实施例形成绝缘层16以及停止层18之前，基底10 上的盖层14是全面性覆盖的，尚未被图案化，而是后续与绝缘层16和停止层18一同被图案化，形成仅覆盖凸起结构12的顶面12a和侧壁12b并延伸覆盖部分主表面10a的盖层14、绝缘层16和停止层18。与第一实施例相比，第二实施例由于省略了一图案化步骤而具有较简化的制作工艺。
请参考图8。首先，类似的，提供一基底10，具有一主表面10a。一凸起结构12，位于主表面10a上。接着，依序形成一盖层14、一绝缘层16以及一停止层18，共型地覆盖主表面10a以及凸起结构12的顶面12a及侧壁 12b。
请参考图9和图10，接着，进行一图案化制作工艺以移除部分盖层14、绝缘层16和停止层18，步骤包含于停止层18上形成一光致抗蚀剂层20，仅覆盖凸起结构12的顶面12a、侧壁12b，以及邻近凸起结构12周围的部分主表面10a，然后以光致抗蚀剂层20为蚀刻掩模进行蚀刻制作工艺，依序移除暴露的停止层18、绝缘层16和盖层14，显露出基底10的主表面10a。如图所示，剩余的停止层18、绝缘层16和盖层14覆盖凸起结构12的顶面 12a、侧壁12b以及邻近凸起结构12周围的部分主表面10a。
请参考图11。接着，全面性地形成一第一介电层22，例如氧化硅，其与基底10直接接触，但不与凸起结构12直接接触。同样的，凸起结构12 的厚度造成第一介电层22在阵列区A和周边区B之间具有一明显的阶梯差 H’。
请参考图12。接着，进行化学机械研磨制作工艺24，移除部分第一介电层22，直到暴露出覆盖凸起结构12顶面12a的停止层18，并得到一平坦的上表面26。
请参考图13和图14。与第一实施例相同，可如图13所示进行一选择性蚀刻制作工艺28，移除暴露的停止层18，或者如图14所示进行一非选择性蚀刻制作工艺29移除暴露的停止层18以及等量的第一介电层22。后续，再全面性地形成预定厚度的第二介电层30，完全覆盖阵列区A和周边区B。
图15至图20为本发明第三实施例的步骤示意图，其中各结构的材质与第一实施例相同，为了简化而与图1至图7使用相同的标记。与第一实施例的主要差异在于，第三实施例的绝缘层16较厚，具体来说，是具有预定厚度，例如第一、第二实施例中第二介电层30的厚度。因此，化学机械研磨制作工艺24并移除暴露的停止层18后，凸起结构12上方仍具有预定厚度的绝缘层16，因此不须再额外形成第二介电层30，相较于第一实施例具有较简化的制作工艺。
请参考图15。首先，提供一基底10，具有一主表面10a。一凸起结构 12，位于主表面10a上。接着，依序形成一预定厚度的绝缘层16以及一停止层18，共型地覆盖主表面10a以及凸起结构12的顶面12a及侧壁12b。根据本发明一实施例，绝缘层16可以包含氧化硅，厚度介于2500埃至3000 埃之间，而停止层18可以包含氮化硅(SiN)、氮氧化硅(SiON)或碳氮化硅(SiCN)，厚度小于或等于100埃，较佳介于50埃至100埃之间。类似的，形成绝缘层16以及停止层18之前，可包含形成一盖层14，覆盖凸起结构 12的顶面12a和侧壁12b并延伸至邻近凸起结构12周围的部分主表面10a。
请参考图16和图17。接着，进行一图案化制作工艺以移除部分停止层 18，步骤包含于停止层18上形成一光致抗蚀剂层20，仅覆盖凸起结构12 的顶面12a，暴露出位于侧壁12b和主表面10a上的停止层18，然后以光致抗蚀剂层20为蚀刻掩模进行蚀刻制作工艺，移除暴露的停止层18，使剩余的停止层18仅覆盖凸起结构12的顶面12a。绝缘层16并不会被蚀刻移除，仍覆盖住凸起结构12的顶面12a、侧壁12b和基底10的主表面10a。
请参考图18。接着，全面性地形成一第一介电层22，例如氧化硅，厚度至少大于凸起结构12的厚度，较佳约是凸起结构12厚度的两倍，以提供后续化学机械研磨制作工艺24足够的研磨厚度。由于绝缘层16的关系，第一介电层22并不会与凸起结构12和基底10直接接触。凸起结构12的厚度造成第一介电层22在阵列区A和周边区B之间具有一明显的阶梯差H。
请参考图19。接着，进行化学机械研磨制作工艺24，移除部分第一介电层22，直到暴露出停止层18，并得到一平坦的上表面26。
请参考图20。后续，可进行一非选择性蚀刻制作工艺29，例如干蚀刻制作工艺或非选择性研磨制作工艺，移除暴露的停止层18以及等量的第一介电层22，显露出覆盖凸起结构12顶面12a的绝缘层16。如前所述，本实施例的绝缘层16已具备预定厚度，因此并不需要额外沉积第二介电层30。制作工艺至此，凸起结构12顶面12a是仅由绝缘层16覆盖，以提供隔离与保护的功能。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (17)

1.一种平坦化方法，包含:
提供一基底，具有一主表面；
凸起结构，位于该主表面上，其中该凸起结构包含一存储器的冠式电容；
形成一绝缘层，共型地覆盖该主表面以及该凸起结构的顶面及侧壁；
在该绝缘层上形成一停止层，至少覆盖该凸起结构的顶面；
全面性地形成一第一介电层，该第一介电层的厚度至少大于该凸起结构的厚度；
进行一化学机械研磨制作工艺，移除部分该第一介电层直到暴露出该停止层，得到一平坦的上表面；
形成一预定厚度的第二介电层，覆盖该上表面。
2.如权利要求1所述的平坦化方法，其中该停止层于该化学机械研磨制作工艺中的移除率小于该第一介电层于该化学机械研磨制作工艺中的移除率的十分之一。
3.如权利要求1所述的平坦化方法，其中该停止层的材料包含氮化硅、氮氧化硅或碳氮化硅，该第一介电层的材料包含氧化硅。
4.如权利要求1所述的平坦化方法，其中形成该第二介电层之前，另包含移除暴露的该停止层。
5.如权利要求1所述的平坦化方法，其中形成该第二介电层之后，另包含进行一缓冲研磨制作工艺。
6.如权利要求1所述的平坦化方法，其中该停止层仅覆盖该凸起结构的顶面。
7.如权利要求6所述的平坦化方法，其中该第一介电层通过该绝缘层而与该凸起结构和该基底完全区隔开。
8.如权利要求1所述的平坦化方法，其中该停止层覆盖该凸起结构的顶面和侧壁，以及该凸起结构周围的部分该主表面。
9.如权利要求8所述的平坦化方法，其中形成该停止层的步骤包含移除未被该停止层覆盖的该绝缘层，暴露出部分该主表面。
10.如权利要求9所述的平坦化方法，其中该暴露的主表面与该第一介电层直接接触。
11.如权利要求1所述的平坦化方法，其中该绝缘层以及该停止层的厚度分别小于或等于100埃。
12.一种平坦化方法，包含:
提供一基底，具有一主表面；
凸起结构，位于该主表面上，其中该凸起结构包含一存储器的冠式电容；
形成一预定厚度的绝缘层，共型地覆盖该主表面以及该凸起结构的顶面及侧壁；
在该绝缘层上形成一停止层，仅覆盖该凸起结构的顶面；
全面性地形成一第一介电层，该第一介电层的厚度至少大于该凸起结构的厚度；
进行一化学机械研磨制作工艺，移除部分该第一介电层直到暴露出该停止层，得到一平坦的上表面。
13.如权利要求12所述的平坦化方法，另包含移除该停止层，暴露出覆盖该凸起结构顶面的该绝缘层。
14.如权利要求12所述的平坦化方法，其中该停止层于该化学机械研磨制作工艺中的移除率小于该第一介电层于该化学机械研磨制作工艺中的移除率的十分之一。
15.如权利要求12所述的平坦化方法，其中该停止层的材料包含氮化硅、氮氧化硅或碳氮化硅，该第一介电层的材料包含氧化硅。
16.如权利要求12所述的平坦化方法，其中移除该停止层时也会等量地移除该停止层及部分该第一介电层。
17.如权利要求12所述的平坦化方法，其中该凸起结构以及该基底通过该绝缘层而与该第一介电层完全区隔开。
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