JP2000137983A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JP2000137983A
JP2000137983A JP23282899A JP23282899A JP2000137983A JP 2000137983 A JP2000137983 A JP 2000137983A JP 23282899 A JP23282899 A JP 23282899A JP 23282899 A JP23282899 A JP 23282899A JP 2000137983 A JP2000137983 A JP 2000137983A
Authority
JP
Japan
Prior art keywords
write
write operation
read
circuit
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23282899A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000137983A5 (https=
Inventor
Kenji Tsuchida
賢二 土田
Haruki Toda
春希 戸田
Hitoshi Kuyama
均 久山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23282899A priority Critical patent/JP2000137983A/ja
Priority to US09/383,193 priority patent/US6484246B2/en
Publication of JP2000137983A publication Critical patent/JP2000137983A/ja
Priority to US10/175,085 priority patent/US6647478B2/en
Priority to US10/337,977 priority patent/US6615309B2/en
Priority to US10/681,184 priority patent/US7085881B2/en
Publication of JP2000137983A5 publication Critical patent/JP2000137983A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Dram (AREA)
  • Read Only Memory (AREA)
JP23282899A 1998-08-26 1999-08-19 半導体記憶装置 Pending JP2000137983A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP23282899A JP2000137983A (ja) 1998-08-26 1999-08-19 半導体記憶装置
US09/383,193 US6484246B2 (en) 1998-08-26 1999-08-26 High-speed random access semiconductor memory device
US10/175,085 US6647478B2 (en) 1998-08-26 2002-06-20 Semiconductor memory device
US10/337,977 US6615309B2 (en) 1998-08-26 2003-01-08 Semiconductor memory device
US10/681,184 US7085881B2 (en) 1998-08-26 2003-10-09 Semiconductor memory device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP10-240161 1998-08-26
JP24016198 1998-08-26
JP23282899A JP2000137983A (ja) 1998-08-26 1999-08-19 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2000137983A true JP2000137983A (ja) 2000-05-16
JP2000137983A5 JP2000137983A5 (https=) 2006-10-05

Family

ID=26530687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23282899A Pending JP2000137983A (ja) 1998-08-26 1999-08-19 半導体記憶装置

Country Status (2)

Country Link
US (4) US6484246B2 (https=)
JP (1) JP2000137983A (https=)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260178A (ja) * 1998-10-30 2000-09-22 Fujitsu Ltd 半導体記憶装置
JP2002251319A (ja) * 2001-02-21 2002-09-06 Fujitsu Ltd 半導体記憶装置および情報処理装置
JP2004502267A (ja) * 2000-07-07 2004-01-22 モサイド・テクノロジーズ・インコーポレイテッド アクセス待ち時間が均一な高速ｄｒａｍアーキテクチャ
JP2006012374A (ja) * 2004-05-26 2006-01-12 Nec Electronics Corp 半導体記憶装置
WO2007013491A1 (ja) * 2005-07-29 2007-02-01 International Business Machines Corporation メモリの制御方法、メモリ・システム
KR100816631B1 (ko) * 2002-01-31 2008-03-24 후지쯔 가부시끼가이샤 반도체 기억장치
JP2008234818A (ja) * 2007-03-22 2008-10-02 Hynix Semiconductor Inc 半導体メモリ装置
US8473705B2 (en) 2008-11-05 2013-06-25 Sanyo Electric Co., Ltd. Memory access apparatus
JP2014017034A (ja) * 2012-07-09 2014-01-30 Renesas Electronics Corp 半導体記憶回路及びその動作方法
JP2021125228A (ja) * 2020-02-03 2021-08-30 インテル・コーポレーション 不揮発性メモリにおける構成可能な書込みコマンド遅延

Families Citing this family (33)

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US6295231B1 (en) * 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
TW522399B (en) * 1999-12-08 2003-03-01 Hitachi Ltd Semiconductor device
JP4083944B2 (ja) 1999-12-13 2008-04-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
KR100644597B1 (ko) * 2000-08-05 2006-11-10 삼성전자주식회사 버스 시스템 및 그 커맨드 전달방법
KR100368117B1 (ko) * 2000-12-28 2003-01-15 삼성전자 주식회사 레이트 선택 동기 파이프라인 타입 반도체 메모리장치에서의 데이터 코히런시 유지방법 및 그에 따른데이터 코히런시 유지회로
US7043598B2 (en) * 2001-12-31 2006-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for dynamic memory refreshing
US7103126B2 (en) * 2002-01-17 2006-09-05 Micron Technology, Inc. Method and circuit for adjusting the timing of output data based on the current and future states of the output data
US7565509B2 (en) * 2002-04-17 2009-07-21 Microsoft Corporation Using limits on address translation to control access to an addressable entity
JP2003331578A (ja) * 2002-05-14 2003-11-21 Toshiba Corp メモリシステム及びそのデータ書き込み方法
US6934199B2 (en) 2002-12-11 2005-08-23 Micron Technology, Inc. Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
US7099221B2 (en) 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20060010339A1 (en) 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
KR100608882B1 (ko) * 2004-06-30 2006-08-08 엘지전자 주식회사 무전극 조명기기의 도파관 시스템
US7254864B2 (en) * 2004-07-01 2007-08-14 Royal Appliance Mfg. Co. Hard floor cleaner
US7116602B2 (en) 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
JP5007485B2 (ja) * 2004-08-26 2012-08-22 ソニー株式会社 半導体記憶装置およびそのアクセス方法、並びにメモリ制御システム
US6965537B1 (en) 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
KR100564633B1 (ko) * 2004-09-25 2006-03-28 삼성전자주식회사 향상된 동작 성능을 가지는 반도체 메모리 장치 및 이에대한 액세스 제어 방법
JP2007036425A (ja) * 2005-07-25 2007-02-08 Pentax Corp アナログ機器駆動システムおよび撮像装置
US7403446B1 (en) 2005-09-27 2008-07-22 Cypress Semiconductor Corporation Single late-write for standard synchronous SRAMs
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
KR100945794B1 (ko) * 2008-05-02 2010-03-08 주식회사 하이닉스반도체 반도체 집적회로 및 그 어드레스/커맨드 처리방법
JP2011100442A (ja) * 2009-10-06 2011-05-19 Semiconductor Energy Lab Co Ltd 無線通信機能を有する半導体装置
KR101043726B1 (ko) * 2009-10-06 2011-06-24 주식회사 하이닉스반도체 반도체 메모리장치 및 이의 동작방법
DE102009051200B4 (de) * 2009-10-29 2014-06-18 Siemens Medical Instruments Pte. Ltd. Hörgerät und Verfahren zur Rückkopplungsunterdrückung mit einem Richtmikrofon
US8250298B2 (en) * 2010-05-27 2012-08-21 International Business Machines Corporation Mechanisms for reducing DRAM power consumption
WO2013046734A1 (ja) * 2011-09-27 2013-04-04 三菱電機株式会社 スレーブ装置、マスター装置及び通信方法
US10607671B2 (en) * 2018-02-17 2020-03-31 Micron Technology, Inc. Timing circuit for command path in a memory device
US10896133B2 (en) * 2018-05-31 2021-01-19 Microsoft Technology Licensing, Llc Combinational address repair in memory controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10255475A (ja) * 1997-03-11 1998-09-25 Hitachi Ltd 半導体記憶装置

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US4360903A (en) * 1980-09-10 1982-11-23 Mostek Corporation Clocking system for a self-refreshed dynamic memory
JP2740097B2 (ja) 1992-03-19 1998-04-15 株式会社東芝 クロック同期型半導体記憶装置およびそのアクセス方法
US5430676A (en) * 1993-06-02 1995-07-04 Rambus, Inc. Dynamic random access memory system
JP3099931B2 (ja) 1993-09-29 2000-10-16 株式会社東芝 半導体装置
JP3170146B2 (ja) 1994-07-29 2001-05-28 株式会社東芝 半導体記憶装置
JP3184096B2 (ja) 1995-08-31 2001-07-09 株式会社東芝 半導体記憶装置
TW348266B (en) 1996-03-11 1998-12-21 Toshiba Co Ltd Semiconductor memory device
JP2888201B2 (ja) 1996-07-30 1999-05-10 日本電気株式会社 半導体メモリ集積回路
US6044429A (en) * 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
JPH1153887A (ja) 1997-08-06 1999-02-26 Toshiba Corp デコード信号比較回路
JPH11306751A (ja) 1998-04-22 1999-11-05 Toshiba Corp 半導体記憶装置
JP4226686B2 (ja) 1998-05-07 2009-02-18 株式会社東芝 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ
US6295231B1 (en) 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
JP4555416B2 (ja) * 1999-09-22 2010-09-29 富士通セミコンダクター株式会社 半導体集積回路およびその制御方法
TW522399B (en) * 1999-12-08 2003-03-01 Hitachi Ltd Semiconductor device
US6151236A (en) * 2000-02-29 2000-11-21 Enhanced Memory Systems, Inc. Enhanced bus turnaround integrated circuit dynamic random access memory device
US6275437B1 (en) * 2000-06-30 2001-08-14 Samsung Electronics Co., Ltd. Refresh-type memory with zero write recovery time and no maximum cycle time

Patent Citations (1)

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JPH10255475A (ja) * 1997-03-11 1998-09-25 Hitachi Ltd 半導体記憶装置

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260178A (ja) * 1998-10-30 2000-09-22 Fujitsu Ltd 半導体記憶装置
US8503250B2 (en) 2000-07-07 2013-08-06 Mosaid Technologies Incorporated High speed DRAM architecture with uniform access latency
JP2004502267A (ja) * 2000-07-07 2004-01-22 モサイド・テクノロジーズ・インコーポレイテッド アクセス待ち時間が均一な高速ｄｒａｍアーキテクチャ
US8045413B2 (en) 2000-07-07 2011-10-25 Mosaid Technologies Incorporated High speed DRAM architecture with uniform access latency
JP2002251319A (ja) * 2001-02-21 2002-09-06 Fujitsu Ltd 半導体記憶装置および情報処理装置
KR100816631B1 (ko) * 2002-01-31 2008-03-24 후지쯔 가부시끼가이샤 반도체 기억장치
JP2006012374A (ja) * 2004-05-26 2006-01-12 Nec Electronics Corp 半導体記憶装置
WO2007013491A1 (ja) * 2005-07-29 2007-02-01 International Business Machines Corporation メモリの制御方法、メモリ・システム
US7843742B2 (en) 2005-07-29 2010-11-30 International Business Machines Corporation Method of controlling memory and memory system thereof
JP2008234818A (ja) * 2007-03-22 2008-10-02 Hynix Semiconductor Inc 半導体メモリ装置
US8320197B2 (en) 2007-03-22 2012-11-27 Hynix Semiconductor Inc. Semiconductor memory device
US8473705B2 (en) 2008-11-05 2013-06-25 Sanyo Electric Co., Ltd. Memory access apparatus
JP2014017034A (ja) * 2012-07-09 2014-01-30 Renesas Electronics Corp 半導体記憶回路及びその動作方法
US9311180B2 (en) 2012-07-09 2016-04-12 Renesas Electronics Corporation Semiconductor storage circuit and operation method thereof
JP2021125228A (ja) * 2020-02-03 2021-08-30 インテル・コーポレーション 不揮発性メモリにおける構成可能な書込みコマンド遅延

Also Published As

Publication number Publication date
US7085881B2 (en) 2006-08-01
US20040078515A1 (en) 2004-04-22
US20030105916A1 (en) 2003-06-05
US20020161981A1 (en) 2002-10-31
US6647478B2 (en) 2003-11-11
US20020078294A1 (en) 2002-06-20
US6484246B2 (en) 2002-11-19
US6615309B2 (en) 2003-09-02

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