JP2000137983A5 - - Google Patents
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- Publication number
- JP2000137983A5 JP2000137983A5 JP1999232828A JP23282899A JP2000137983A5 JP 2000137983 A5 JP2000137983 A5 JP 2000137983A5 JP 1999232828 A JP1999232828 A JP 1999232828A JP 23282899 A JP23282899 A JP 23282899A JP 2000137983 A5 JP2000137983 A5 JP 2000137983A5
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- write operation
- write
- information
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 description 8
- 230000003111 delayed effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 238000001994 activation Methods 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 1
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23282899A JP2000137983A (ja) | 1998-08-26 | 1999-08-19 | 半導体記憶装置 |
| US09/383,193 US6484246B2 (en) | 1998-08-26 | 1999-08-26 | High-speed random access semiconductor memory device |
| US10/175,085 US6647478B2 (en) | 1998-08-26 | 2002-06-20 | Semiconductor memory device |
| US10/337,977 US6615309B2 (en) | 1998-08-26 | 2003-01-08 | Semiconductor memory device |
| US10/681,184 US7085881B2 (en) | 1998-08-26 | 2003-10-09 | Semiconductor memory device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10-240161 | 1998-08-26 | ||
| JP24016198 | 1998-08-26 | ||
| JP23282899A JP2000137983A (ja) | 1998-08-26 | 1999-08-19 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000137983A JP2000137983A (ja) | 2000-05-16 |
| JP2000137983A5 true JP2000137983A5 (https=) | 2006-10-05 |
Family
ID=26530687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23282899A Pending JP2000137983A (ja) | 1998-08-26 | 1999-08-19 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (4) | US6484246B2 (https=) |
| JP (1) | JP2000137983A (https=) |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6295231B1 (en) * | 1998-07-17 | 2001-09-25 | Kabushiki Kaisha Toshiba | High-speed cycle clock-synchronous memory device |
| JP4817477B2 (ja) * | 1998-10-30 | 2011-11-16 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
| US6643787B1 (en) * | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
| TW522399B (en) * | 1999-12-08 | 2003-03-01 | Hitachi Ltd | Semiconductor device |
| JP4083944B2 (ja) | 1999-12-13 | 2008-04-30 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
| JP2004502267A (ja) | 2000-07-07 | 2004-01-22 | モサイド・テクノロジーズ・インコーポレイテッド | アクセス待ち時間が均一な高速dramアーキテクチャ |
| KR100644597B1 (ko) * | 2000-08-05 | 2006-11-10 | 삼성전자주식회사 | 버스 시스템 및 그 커맨드 전달방법 |
| KR100368117B1 (ko) * | 2000-12-28 | 2003-01-15 | 삼성전자 주식회사 | 레이트 선택 동기 파이프라인 타입 반도체 메모리장치에서의 데이터 코히런시 유지방법 및 그에 따른데이터 코히런시 유지회로 |
| JP4651206B2 (ja) * | 2001-02-21 | 2011-03-16 | 富士通セミコンダクター株式会社 | 半導体記憶装置および情報処理装置 |
| US7043598B2 (en) * | 2001-12-31 | 2006-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for dynamic memory refreshing |
| US7103126B2 (en) * | 2002-01-17 | 2006-09-05 | Micron Technology, Inc. | Method and circuit for adjusting the timing of output data based on the current and future states of the output data |
| JP2003228978A (ja) * | 2002-01-31 | 2003-08-15 | Fujitsu Ltd | 半導体記憶装置 |
| US7565509B2 (en) * | 2002-04-17 | 2009-07-21 | Microsoft Corporation | Using limits on address translation to control access to an addressable entity |
| JP2003331578A (ja) * | 2002-05-14 | 2003-11-21 | Toshiba Corp | メモリシステム及びそのデータ書き込み方法 |
| US6934199B2 (en) | 2002-12-11 | 2005-08-23 | Micron Technology, Inc. | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency |
| US7099221B2 (en) | 2004-05-06 | 2006-08-29 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
| JP4827399B2 (ja) * | 2004-05-26 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US20060010339A1 (en) | 2004-06-24 | 2006-01-12 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
| US7340668B2 (en) | 2004-06-25 | 2008-03-04 | Micron Technology, Inc. | Low power cost-effective ECC memory system and method |
| KR100608882B1 (ko) * | 2004-06-30 | 2006-08-08 | 엘지전자 주식회사 | 무전극 조명기기의 도파관 시스템 |
| US7254864B2 (en) * | 2004-07-01 | 2007-08-14 | Royal Appliance Mfg. Co. | Hard floor cleaner |
| US7116602B2 (en) | 2004-07-15 | 2006-10-03 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
| US8190808B2 (en) * | 2004-08-17 | 2012-05-29 | Rambus Inc. | Memory device having staggered memory operations |
| JP5007485B2 (ja) * | 2004-08-26 | 2012-08-22 | ソニー株式会社 | 半導体記憶装置およびそのアクセス方法、並びにメモリ制御システム |
| US6965537B1 (en) | 2004-08-31 | 2005-11-15 | Micron Technology, Inc. | Memory system and method using ECC to achieve low power refresh |
| KR100564633B1 (ko) * | 2004-09-25 | 2006-03-28 | 삼성전자주식회사 | 향상된 동작 성능을 가지는 반도체 메모리 장치 및 이에대한 액세스 제어 방법 |
| JP2007036425A (ja) * | 2005-07-25 | 2007-02-08 | Pentax Corp | アナログ機器駆動システムおよび撮像装置 |
| TWI410970B (zh) | 2005-07-29 | 2013-10-01 | Ibm | 控制記憶體的方法及記憶體系統 |
| US7403446B1 (en) | 2005-09-27 | 2008-07-22 | Cypress Semiconductor Corporation | Single late-write for standard synchronous SRAMs |
| US7894289B2 (en) | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
| US7900120B2 (en) | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
| KR100868251B1 (ko) | 2007-03-22 | 2008-11-12 | 주식회사 하이닉스반도체 | 반도체 메모리장치 |
| KR100945794B1 (ko) * | 2008-05-02 | 2010-03-08 | 주식회사 하이닉스반도체 | 반도체 집적회로 및 그 어드레스/커맨드 처리방법 |
| JP2010113435A (ja) | 2008-11-05 | 2010-05-20 | Sanyo Electric Co Ltd | メモリアクセス装置 |
| JP2011100442A (ja) * | 2009-10-06 | 2011-05-19 | Semiconductor Energy Lab Co Ltd | 無線通信機能を有する半導体装置 |
| KR101043726B1 (ko) * | 2009-10-06 | 2011-06-24 | 주식회사 하이닉스반도체 | 반도체 메모리장치 및 이의 동작방법 |
| DE102009051200B4 (de) * | 2009-10-29 | 2014-06-18 | Siemens Medical Instruments Pte. Ltd. | Hörgerät und Verfahren zur Rückkopplungsunterdrückung mit einem Richtmikrofon |
| US8250298B2 (en) * | 2010-05-27 | 2012-08-21 | International Business Machines Corporation | Mechanisms for reducing DRAM power consumption |
| WO2013046734A1 (ja) * | 2011-09-27 | 2013-04-04 | 三菱電機株式会社 | スレーブ装置、マスター装置及び通信方法 |
| JP6072449B2 (ja) | 2012-07-09 | 2017-02-01 | ルネサスエレクトロニクス株式会社 | 半導体記憶回路及びその動作方法 |
| US10607671B2 (en) * | 2018-02-17 | 2020-03-31 | Micron Technology, Inc. | Timing circuit for command path in a memory device |
| US10896133B2 (en) * | 2018-05-31 | 2021-01-19 | Microsoft Technology Licensing, Llc | Combinational address repair in memory controller |
| US11188264B2 (en) * | 2020-02-03 | 2021-11-30 | Intel Corporation | Configurable write command delay in nonvolatile memory |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4360903A (en) * | 1980-09-10 | 1982-11-23 | Mostek Corporation | Clocking system for a self-refreshed dynamic memory |
| JP2740097B2 (ja) | 1992-03-19 | 1998-04-15 | 株式会社東芝 | クロック同期型半導体記憶装置およびそのアクセス方法 |
| US5430676A (en) * | 1993-06-02 | 1995-07-04 | Rambus, Inc. | Dynamic random access memory system |
| JP3099931B2 (ja) | 1993-09-29 | 2000-10-16 | 株式会社東芝 | 半導体装置 |
| JP3170146B2 (ja) | 1994-07-29 | 2001-05-28 | 株式会社東芝 | 半導体記憶装置 |
| JP3184096B2 (ja) | 1995-08-31 | 2001-07-09 | 株式会社東芝 | 半導体記憶装置 |
| TW348266B (en) | 1996-03-11 | 1998-12-21 | Toshiba Co Ltd | Semiconductor memory device |
| JP2888201B2 (ja) | 1996-07-30 | 1999-05-10 | 日本電気株式会社 | 半導体メモリ集積回路 |
| JP3604861B2 (ja) * | 1997-03-11 | 2004-12-22 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US6044429A (en) * | 1997-07-10 | 2000-03-28 | Micron Technology, Inc. | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths |
| JPH1153887A (ja) | 1997-08-06 | 1999-02-26 | Toshiba Corp | デコード信号比較回路 |
| JPH11306751A (ja) | 1998-04-22 | 1999-11-05 | Toshiba Corp | 半導体記憶装置 |
| JP4226686B2 (ja) | 1998-05-07 | 2009-02-18 | 株式会社東芝 | 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ |
| US6295231B1 (en) | 1998-07-17 | 2001-09-25 | Kabushiki Kaisha Toshiba | High-speed cycle clock-synchronous memory device |
| JP4555416B2 (ja) * | 1999-09-22 | 2010-09-29 | 富士通セミコンダクター株式会社 | 半導体集積回路およびその制御方法 |
| TW522399B (en) * | 1999-12-08 | 2003-03-01 | Hitachi Ltd | Semiconductor device |
| US6151236A (en) * | 2000-02-29 | 2000-11-21 | Enhanced Memory Systems, Inc. | Enhanced bus turnaround integrated circuit dynamic random access memory device |
| US6275437B1 (en) * | 2000-06-30 | 2001-08-14 | Samsung Electronics Co., Ltd. | Refresh-type memory with zero write recovery time and no maximum cycle time |
-
1999
- 1999-08-19 JP JP23282899A patent/JP2000137983A/ja active Pending
- 1999-08-26 US US09/383,193 patent/US6484246B2/en not_active Expired - Lifetime
-
2002
- 2002-06-20 US US10/175,085 patent/US6647478B2/en not_active Expired - Fee Related
-
2003
- 2003-01-08 US US10/337,977 patent/US6615309B2/en not_active Expired - Fee Related
- 2003-10-09 US US10/681,184 patent/US7085881B2/en not_active Expired - Fee Related
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