JP2000076853A - 同期型半導体記憶装置 - Google Patents

同期型半導体記憶装置

Info

Publication number
JP2000076853A
JP2000076853A JP10269761A JP26976198A JP2000076853A JP 2000076853 A JP2000076853 A JP 2000076853A JP 10269761 A JP10269761 A JP 10269761A JP 26976198 A JP26976198 A JP 26976198A JP 2000076853 A JP2000076853 A JP 2000076853A
Authority
JP
Japan
Prior art keywords
data
circuit
output
input
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10269761A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000076853A5 (enExample
Inventor
Tsukasa Oishi
司 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26493088&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2000076853(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10269761A priority Critical patent/JP2000076853A/ja
Priority to US09/266,918 priority patent/US6324118B1/en
Priority to KR1019990017539A priority patent/KR100357022B1/ko
Publication of JP2000076853A publication Critical patent/JP2000076853A/ja
Priority to US09/833,735 priority patent/US6330200B2/en
Priority to US09/986,111 priority patent/US6522598B2/en
Publication of JP2000076853A5 publication Critical patent/JP2000076853A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP10269761A 1998-06-17 1998-09-24 同期型半導体記憶装置 Pending JP2000076853A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP10269761A JP2000076853A (ja) 1998-06-17 1998-09-24 同期型半導体記憶装置
US09/266,918 US6324118B1 (en) 1998-06-17 1999-03-12 Synchronous semiconductor memory device having improved operational frequency margin at data input/output
KR1019990017539A KR100357022B1 (ko) 1998-06-17 1999-05-17 데이타 입출력시의 동작 주파수 마진이 개선된 동기형 반도체기억 장치
US09/833,735 US6330200B2 (en) 1998-06-17 2001-04-13 Synchronous semiconductor memory device having improved operational frequency margin at data input/output
US09/986,111 US6522598B2 (en) 1998-06-17 2001-11-07 Synchronous semiconductor memory device having improved operational frequency margin at data input/output

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP10-169881 1998-06-17
JP16988198 1998-06-17
JP10269761A JP2000076853A (ja) 1998-06-17 1998-09-24 同期型半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2000076853A true JP2000076853A (ja) 2000-03-14
JP2000076853A5 JP2000076853A5 (enExample) 2005-10-27

Family

ID=26493088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10269761A Pending JP2000076853A (ja) 1998-06-17 1998-09-24 同期型半導体記憶装置

Country Status (3)

Country Link
US (3) US6324118B1 (enExample)
JP (1) JP2000076853A (enExample)
KR (1) KR100357022B1 (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001297595A (ja) * 2000-04-13 2001-10-26 Mitsubishi Electric Corp 半導体記憶装置及び半導体集積回路装置
WO2002089141A1 (en) * 2001-03-14 2002-11-07 Micron Technology, Inc. Multiple bit prefetch output data path
EP1136834A3 (de) * 2000-03-23 2005-01-19 Infineon Technologies AG Integrierte Schaltung mit Ansteuerungsschaltung zur Ansteuerung einer Treiberschaltung
EP1176606A3 (de) * 2000-07-18 2006-05-10 Infineon Technologies AG Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen
CN100527267C (zh) * 2006-02-28 2009-08-12 中国科学院计算技术研究所 Ddr和ddr2内存控制器的读数据采样方法及装置
JP2010040082A (ja) * 2008-08-01 2010-02-18 Elpida Memory Inc 半導体記憶装置及び半導体記憶装置のテスト方法

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US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
JP4011833B2 (ja) * 2000-06-30 2007-11-21 株式会社東芝 半導体メモリ
JP4600792B2 (ja) * 2000-07-13 2010-12-15 エルピーダメモリ株式会社 半導体装置
US6732305B2 (en) * 2000-10-05 2004-05-04 United Memories, Inc. Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry
JP4592179B2 (ja) * 2000-12-19 2010-12-01 ルネサスエレクトロニクス株式会社 ディレイロックドループ、当該ディレイロックドループを含む半導体装置およびクロック同期により動作するシステムのための制御方法
JP2003045200A (ja) * 2001-08-02 2003-02-14 Mitsubishi Electric Corp 半導体モジュールおよびそれに用いる半導体記憶装置
DE10146149B4 (de) * 2001-09-19 2004-04-29 Infineon Technologies Ag Schaltungsanordnung zum Empfang eines Datensignals
KR100403635B1 (ko) * 2001-11-06 2003-10-30 삼성전자주식회사 동기식 반도체 메모리 장치의 데이터 입력 회로 및 데이터입력 방법
JP3657234B2 (ja) * 2002-03-08 2005-06-08 Ｎｅｃマイクロシステム株式会社 非同期インタフェース装置及び非同期インタフェース方法
US6728156B2 (en) * 2002-03-11 2004-04-27 International Business Machines Corporation Memory array system
KR100482736B1 (ko) * 2002-09-12 2005-04-14 주식회사 하이닉스반도체 지연고정루프의 지연 모델 및 그의 튜닝 방법
JP2004178729A (ja) * 2002-11-28 2004-06-24 Hitachi Ltd 半導体記憶装置
KR20040067512A (ko) * 2003-01-23 2004-07-30 삼성전자주식회사 데이터 통신 시스템의 클럭 모니터링 장치
US6931479B2 (en) * 2003-03-04 2005-08-16 Micron Technology, Inc. Method and apparatus for multi-functional inputs of a memory device
JP4327482B2 (ja) * 2003-03-18 2009-09-09 富士通マイクロエレクトロニクス株式会社 同期型半導体記憶装置
JP2005078592A (ja) * 2003-09-03 2005-03-24 Brother Ind Ltd メモリ制御装置及び画像形成装置
US7143257B2 (en) * 2003-10-14 2006-11-28 Atmel Corporation Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system
US6995554B2 (en) * 2004-06-16 2006-02-07 Agilent Technologies, Inc. Delay-locked loop and a method of testing a delay-locked loop
US7126874B2 (en) * 2004-08-31 2006-10-24 Micron Technology, Inc. Memory system and method for strobing data, command and address signals
US7212464B2 (en) * 2004-09-17 2007-05-01 Seiko Epson Corporation Semiconductor memory device having a plurality of latch circuits coupled to each read amplifier
KR100608371B1 (ko) * 2004-12-03 2006-08-08 주식회사 하이닉스반도체 메모리 장치의 데이타 출력 제어 방법 및 그 장치
US7461365B1 (en) * 2005-07-09 2008-12-02 Lightspeed Logic, Inc. Increased effective flip-flop density in a structured ASIC
JP2007064648A (ja) * 2005-08-29 2007-03-15 Nec Electronics Corp 半導体集積回路及びテスト方法
US7307913B2 (en) * 2005-09-29 2007-12-11 Hynix Semiconductor Inc. Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption
KR100812600B1 (ko) * 2005-09-29 2008-03-13 주식회사 하이닉스반도체 주파수가 다른 복수의 클럭을 사용하는 반도체메모리소자
US8332793B2 (en) * 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
JP2008009991A (ja) * 2006-06-29 2008-01-17 Hynix Semiconductor Inc テスト用デュアルインラインメモリモジュール及びそのテストシステム
US7554858B2 (en) 2007-08-10 2009-06-30 Micron Technology, Inc. System and method for reducing pin-count of memory devices, and memory device testers for same
KR101529291B1 (ko) 2008-02-27 2015-06-17 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 플래시 메모리시스템
US7881127B2 (en) 2008-05-20 2011-02-01 Hynix Semiconductor Inc. Nonvolatile memory device and method of testing the same
KR100991308B1 (ko) 2008-05-20 2010-11-01 주식회사 하이닉스반도체 불휘발성 메모리 소자 및 그 테스트 방법
US20090296514A1 (en) * 2008-05-29 2009-12-03 Chih-Hui Yeh Method for accessing a memory chip
JP5687412B2 (ja) 2009-01-16 2015-03-18 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びそのリード待ち時間調整方法、メモリシステム、並びに半導体装置
JP5627197B2 (ja) 2009-05-26 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びこれを備える情報処理システム並びにコントローラ
JP2012112788A (ja) * 2010-11-24 2012-06-14 Seiko Instruments Inc テストモード設定回路
KR20130050776A (ko) * 2011-11-08 2013-05-16 에스케이하이닉스 주식회사 반도체 장치와 반도체 장치를 포함하는 반도체 시스템 및 그 동작방법
US8934317B2 (en) * 2012-01-13 2015-01-13 Samsung Electronics Co., Ltd. Semiconductor memory devices having internal clock signals and memory systems including such memory devices
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US9749555B2 (en) * 2014-02-04 2017-08-29 Semiconductor Components Industries, Llc Arithmetic memory with horizontal binning capabilities for imaging systems
KR20160075175A (ko) * 2014-12-19 2016-06-29 에스케이하이닉스 주식회사 반도체 장치
US11487871B2 (en) * 2015-01-31 2022-11-01 San Diego Gas & Electric Company Methods and systems for detecting and defending against invalid time signals
US20160342540A1 (en) * 2015-05-21 2016-11-24 Qualcomm Innovation Center, Inc. Low latency memory and bus frequency scaling based upon hardware monitoring
KR102337044B1 (ko) * 2015-07-27 2021-12-09 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10474779B1 (en) * 2017-09-22 2019-11-12 Juniper Networks, Inc. Bisection methodology for on-chip variation tolerant clock signal distribution in an integrated circuit
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KR20190058158A (ko) * 2017-11-21 2019-05-29 삼성전자주식회사 데이터 출력 회로, 데이터 출력 회로를 포함하는 메모리 장치 및 메모리 장치의 동작 방법
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US10395702B1 (en) * 2018-05-11 2019-08-27 Micron Technology, Inc. Memory device with a clocking mechanism
KR102889555B1 (ko) * 2019-08-26 2025-11-24 에스케이하이닉스 주식회사 테스트 회로, 이를 포함하는 반도체 장치 및 테스트 시스템
JP7385419B2 (ja) * 2019-10-15 2023-11-22 ルネサスエレクトロニクス株式会社 半導体装置
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1136834A3 (de) * 2000-03-23 2005-01-19 Infineon Technologies AG Integrierte Schaltung mit Ansteuerungsschaltung zur Ansteuerung einer Treiberschaltung
JP2001297595A (ja) * 2000-04-13 2001-10-26 Mitsubishi Electric Corp 半導体記憶装置及び半導体集積回路装置
EP1176606A3 (de) * 2000-07-18 2006-05-10 Infineon Technologies AG Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen
WO2002089141A1 (en) * 2001-03-14 2002-11-07 Micron Technology, Inc. Multiple bit prefetch output data path
US6556494B2 (en) 2001-03-14 2003-04-29 Micron Technology, Inc. High frequency range four bit prefetch output data path
US6600691B2 (en) 2001-03-14 2003-07-29 Micron Technology, Inc. High frequency range four bit prefetch output data path
CN100565698C (zh) * 2001-03-14 2009-12-02 微米技术有限公司 具有多比特预取输出数据通路的装置及其操作方法
CN100527267C (zh) * 2006-02-28 2009-08-12 中国科学院计算技术研究所 Ddr和ddr2内存控制器的读数据采样方法及装置
JP2010040082A (ja) * 2008-08-01 2010-02-18 Elpida Memory Inc 半導体記憶装置及び半導体記憶装置のテスト方法
US8542546B2 (en) 2008-08-01 2013-09-24 Elpida Memory, Inc. Semiconductor memory device and method for testing same
US8724410B2 (en) 2008-08-01 2014-05-13 Elpida Memory, Inc. Semiconductor memory device and method for testing same

Also Published As

Publication number Publication date
KR20000005666A (ko) 2000-01-25
US6324118B1 (en) 2001-11-27
US20010015927A1 (en) 2001-08-23
US6330200B2 (en) 2001-12-11
US20020039315A1 (en) 2002-04-04
KR100357022B1 (ko) 2002-10-18
US6522598B2 (en) 2003-02-18

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