JP2000076853A5 - - Google Patents

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Publication number
JP2000076853A5
JP2000076853A5 JP1998269761A JP26976198A JP2000076853A5 JP 2000076853 A5 JP2000076853 A5 JP 2000076853A5 JP 1998269761 A JP1998269761 A JP 1998269761A JP 26976198 A JP26976198 A JP 26976198A JP 2000076853 A5 JP2000076853 A5 JP 2000076853A5
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JP
Japan
Prior art keywords
output
data
signal
node
input
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Pending
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JP1998269761A
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English (en)
Japanese (ja)
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JP2000076853A (ja
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Priority to JP10269761A priority Critical patent/JP2000076853A/ja
Priority claimed from JP10269761A external-priority patent/JP2000076853A/ja
Priority to US09/266,918 priority patent/US6324118B1/en
Priority to KR1019990017539A priority patent/KR100357022B1/ko
Publication of JP2000076853A publication Critical patent/JP2000076853A/ja
Priority to US09/833,735 priority patent/US6330200B2/en
Priority to US09/986,111 priority patent/US6522598B2/en
Publication of JP2000076853A5 publication Critical patent/JP2000076853A5/ja
Pending legal-status Critical Current

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JP10269761A 1998-06-17 1998-09-24 同期型半導体記憶装置 Pending JP2000076853A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP10269761A JP2000076853A (ja) 1998-06-17 1998-09-24 同期型半導体記憶装置
US09/266,918 US6324118B1 (en) 1998-06-17 1999-03-12 Synchronous semiconductor memory device having improved operational frequency margin at data input/output
KR1019990017539A KR100357022B1 (ko) 1998-06-17 1999-05-17 데이타 입출력시의 동작 주파수 마진이 개선된 동기형 반도체기억 장치
US09/833,735 US6330200B2 (en) 1998-06-17 2001-04-13 Synchronous semiconductor memory device having improved operational frequency margin at data input/output
US09/986,111 US6522598B2 (en) 1998-06-17 2001-11-07 Synchronous semiconductor memory device having improved operational frequency margin at data input/output

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP10-169881 1998-06-17
JP16988198 1998-06-17
JP10269761A JP2000076853A (ja) 1998-06-17 1998-09-24 同期型半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2000076853A JP2000076853A (ja) 2000-03-14
JP2000076853A5 true JP2000076853A5 (enExample) 2005-10-27

Family

ID=26493088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10269761A Pending JP2000076853A (ja) 1998-06-17 1998-09-24 同期型半導体記憶装置

Country Status (3)

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US (3) US6324118B1 (enExample)
JP (1) JP2000076853A (enExample)
KR (1) KR100357022B1 (enExample)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
DE10014386A1 (de) * 2000-03-23 2001-09-27 Infineon Technologies Ag Integrierte Schaltung mit Ansteuerschaltung zur Ansteuerung einer Treiberschaltung
JP2001297595A (ja) * 2000-04-13 2001-10-26 Mitsubishi Electric Corp 半導体記憶装置及び半導体集積回路装置
JP4011833B2 (ja) * 2000-06-30 2007-11-21 株式会社東芝 半導体メモリ
JP4600792B2 (ja) * 2000-07-13 2010-12-15 エルピーダメモリ株式会社 半導体装置
DE10034852A1 (de) * 2000-07-18 2002-02-07 Infineon Technologies Ag Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen
US6732305B2 (en) * 2000-10-05 2004-05-04 United Memories, Inc. Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry
JP4592179B2 (ja) * 2000-12-19 2010-12-01 ルネサスエレクトロニクス株式会社 ディレイロックドループ、当該ディレイロックドループを含む半導体装置およびクロック同期により動作するシステムのための制御方法
US6556494B2 (en) 2001-03-14 2003-04-29 Micron Technology, Inc. High frequency range four bit prefetch output data path
JP2003045200A (ja) * 2001-08-02 2003-02-14 Mitsubishi Electric Corp 半導体モジュールおよびそれに用いる半導体記憶装置
DE10146149B4 (de) * 2001-09-19 2004-04-29 Infineon Technologies Ag Schaltungsanordnung zum Empfang eines Datensignals
KR100403635B1 (ko) * 2001-11-06 2003-10-30 삼성전자주식회사 동기식 반도체 메모리 장치의 데이터 입력 회로 및 데이터입력 방법
JP3657234B2 (ja) * 2002-03-08 2005-06-08 Ｎｅｃマイクロシステム株式会社 非同期インタフェース装置及び非同期インタフェース方法
US6728156B2 (en) * 2002-03-11 2004-04-27 International Business Machines Corporation Memory array system
KR100482736B1 (ko) * 2002-09-12 2005-04-14 주식회사 하이닉스반도체 지연고정루프의 지연 모델 및 그의 튜닝 방법
JP2004178729A (ja) * 2002-11-28 2004-06-24 Hitachi Ltd 半導体記憶装置
KR20040067512A (ko) * 2003-01-23 2004-07-30 삼성전자주식회사 데이터 통신 시스템의 클럭 모니터링 장치
US6931479B2 (en) * 2003-03-04 2005-08-16 Micron Technology, Inc. Method and apparatus for multi-functional inputs of a memory device
JP4327482B2 (ja) * 2003-03-18 2009-09-09 富士通マイクロエレクトロニクス株式会社 同期型半導体記憶装置
JP2005078592A (ja) * 2003-09-03 2005-03-24 Brother Ind Ltd メモリ制御装置及び画像形成装置
US7143257B2 (en) * 2003-10-14 2006-11-28 Atmel Corporation Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system
US6995554B2 (en) * 2004-06-16 2006-02-07 Agilent Technologies, Inc. Delay-locked loop and a method of testing a delay-locked loop
US7126874B2 (en) * 2004-08-31 2006-10-24 Micron Technology, Inc. Memory system and method for strobing data, command and address signals
US7212464B2 (en) * 2004-09-17 2007-05-01 Seiko Epson Corporation Semiconductor memory device having a plurality of latch circuits coupled to each read amplifier
KR100608371B1 (ko) * 2004-12-03 2006-08-08 주식회사 하이닉스반도체 메모리 장치의 데이타 출력 제어 방법 및 그 장치
US7461365B1 (en) * 2005-07-09 2008-12-02 Lightspeed Logic, Inc. Increased effective flip-flop density in a structured ASIC
JP2007064648A (ja) * 2005-08-29 2007-03-15 Nec Electronics Corp 半導体集積回路及びテスト方法
US7307913B2 (en) * 2005-09-29 2007-12-11 Hynix Semiconductor Inc. Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption
KR100812600B1 (ko) * 2005-09-29 2008-03-13 주식회사 하이닉스반도체 주파수가 다른 복수의 클럭을 사용하는 반도체메모리소자
CN100527267C (zh) * 2006-02-28 2009-08-12 中国科学院计算技术研究所 Ddr和ddr2内存控制器的读数据采样方法及装置
US8332793B2 (en) * 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
JP2008009991A (ja) * 2006-06-29 2008-01-17 Hynix Semiconductor Inc テスト用デュアルインラインメモリモジュール及びそのテストシステム
US7554858B2 (en) 2007-08-10 2009-06-30 Micron Technology, Inc. System and method for reducing pin-count of memory devices, and memory device testers for same
KR101529291B1 (ko) 2008-02-27 2015-06-17 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 플래시 메모리시스템
US7881127B2 (en) 2008-05-20 2011-02-01 Hynix Semiconductor Inc. Nonvolatile memory device and method of testing the same
KR100991308B1 (ko) 2008-05-20 2010-11-01 주식회사 하이닉스반도체 불휘발성 메모리 소자 및 그 테스트 방법
US20090296514A1 (en) * 2008-05-29 2009-12-03 Chih-Hui Yeh Method for accessing a memory chip
JP5579972B2 (ja) * 2008-08-01 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置及び半導体記憶装置のテスト方法
JP5687412B2 (ja) 2009-01-16 2015-03-18 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びそのリード待ち時間調整方法、メモリシステム、並びに半導体装置
JP5627197B2 (ja) 2009-05-26 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びこれを備える情報処理システム並びにコントローラ
JP2012112788A (ja) * 2010-11-24 2012-06-14 Seiko Instruments Inc テストモード設定回路
KR20130050776A (ko) * 2011-11-08 2013-05-16 에스케이하이닉스 주식회사 반도체 장치와 반도체 장치를 포함하는 반도체 시스템 및 그 동작방법
US8934317B2 (en) * 2012-01-13 2015-01-13 Samsung Electronics Co., Ltd. Semiconductor memory devices having internal clock signals and memory systems including such memory devices
US9350386B2 (en) 2012-04-12 2016-05-24 Samsung Electronics Co., Ltd. Memory device, memory system, and method of operating the same
US9749555B2 (en) * 2014-02-04 2017-08-29 Semiconductor Components Industries, Llc Arithmetic memory with horizontal binning capabilities for imaging systems
KR20160075175A (ko) * 2014-12-19 2016-06-29 에스케이하이닉스 주식회사 반도체 장치
US11487871B2 (en) * 2015-01-31 2022-11-01 San Diego Gas & Electric Company Methods and systems for detecting and defending against invalid time signals
US20160342540A1 (en) * 2015-05-21 2016-11-24 Qualcomm Innovation Center, Inc. Low latency memory and bus frequency scaling based upon hardware monitoring
KR102337044B1 (ko) * 2015-07-27 2021-12-09 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10474779B1 (en) * 2017-09-22 2019-11-12 Juniper Networks, Inc. Bisection methodology for on-chip variation tolerant clock signal distribution in an integrated circuit
US10437514B2 (en) * 2017-10-02 2019-10-08 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories
KR20190058158A (ko) * 2017-11-21 2019-05-29 삼성전자주식회사 데이터 출력 회로, 데이터 출력 회로를 포함하는 메모리 장치 및 메모리 장치의 동작 방법
US10915474B2 (en) 2017-11-29 2021-02-09 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories
US10395702B1 (en) * 2018-05-11 2019-08-27 Micron Technology, Inc. Memory device with a clocking mechanism
KR102889555B1 (ko) * 2019-08-26 2025-11-24 에스케이하이닉스 주식회사 테스트 회로, 이를 포함하는 반도체 장치 및 테스트 시스템
JP7385419B2 (ja) * 2019-10-15 2023-11-22 ルネサスエレクトロニクス株式会社 半導体装置
US12334146B1 (en) 2022-09-23 2025-06-17 Apple Inc. Power loss reduction in data storage arrays

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413740A (en) * 1977-07-04 1979-02-01 Nippon Telegr & Teleph Corp <Ntt> Memory unit
JPS62211763A (ja) 1986-03-13 1987-09-17 Fujitsu Ltd 同期出力回路
JP3346827B2 (ja) * 1993-05-25 2002-11-18 三菱電機株式会社 同期型半導体記憶装置
JPH07226100A (ja) * 1994-02-15 1995-08-22 Nec Corp 半導体メモリ装置
JP3577119B2 (ja) 1994-11-01 2004-10-13 株式会社ルネサステクノロジ 半導体記憶装置
JPH08138377A (ja) 1994-11-08 1996-05-31 Hitachi Ltd 半導体記憶装置
JP3252678B2 (ja) 1995-10-20 2002-02-04 日本電気株式会社 同期式半導体メモリ
JPH09223389A (ja) * 1996-02-15 1997-08-26 Mitsubishi Electric Corp 同期型半導体記憶装置
US6072743A (en) * 1998-01-13 2000-06-06 Mitsubishi Denki Kabushiki Kaisha High speed operable semiconductor memory device with memory blocks arranged about the center

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