KR100357022B1 - 데이타 입출력시의 동작 주파수 마진이 개선된 동기형 반도체기억 장치 - Google Patents

데이타 입출력시의 동작 주파수 마진이 개선된 동기형 반도체기억 장치 Download PDF

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Publication number
KR100357022B1
KR100357022B1 KR1019990017539A KR19990017539A KR100357022B1 KR 100357022 B1 KR100357022 B1 KR 100357022B1 KR 1019990017539 A KR1019990017539 A KR 1019990017539A KR 19990017539 A KR19990017539 A KR 19990017539A KR 100357022 B1 KR100357022 B1 KR 100357022B1
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data
circuit
output
input
signal
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KR20000005666A (ko
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오오이시츠카사
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미쓰비시덴키 가부시키가이샤
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

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  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1019990017539A 1998-06-17 1999-05-17 데이타 입출력시의 동작 주파수 마진이 개선된 동기형 반도체기억 장치 Expired - Fee Related KR100357022B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1998-169881 1998-06-17
JP16988198 1998-06-17
JP10269761A JP2000076853A (ja) 1998-06-17 1998-09-24 同期型半導体記憶装置
JP1998-269761 1998-09-24

Publications (2)

Publication Number Publication Date
KR20000005666A KR20000005666A (ko) 2000-01-25
KR100357022B1 true KR100357022B1 (ko) 2002-10-18

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KR1019990017539A Expired - Fee Related KR100357022B1 (ko) 1998-06-17 1999-05-17 데이타 입출력시의 동작 주파수 마진이 개선된 동기형 반도체기억 장치

Country Status (3)

Country Link
US (3) US6324118B1 (enExample)
JP (1) JP2000076853A (enExample)
KR (1) KR100357022B1 (enExample)

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KR100991308B1 (ko) 2008-05-20 2010-11-01 주식회사 하이닉스반도체 불휘발성 메모리 소자 및 그 테스트 방법
US7881127B2 (en) 2008-05-20 2011-02-01 Hynix Semiconductor Inc. Nonvolatile memory device and method of testing the same

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JP4011833B2 (ja) * 2000-06-30 2007-11-21 株式会社東芝 半導体メモリ
JP4600792B2 (ja) * 2000-07-13 2010-12-15 エルピーダメモリ株式会社 半導体装置
DE10034852A1 (de) * 2000-07-18 2002-02-07 Infineon Technologies Ag Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen
US6732305B2 (en) * 2000-10-05 2004-05-04 United Memories, Inc. Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry
JP4592179B2 (ja) * 2000-12-19 2010-12-01 ルネサスエレクトロニクス株式会社 ディレイロックドループ、当該ディレイロックドループを含む半導体装置およびクロック同期により動作するシステムのための制御方法
US6556494B2 (en) 2001-03-14 2003-04-29 Micron Technology, Inc. High frequency range four bit prefetch output data path
JP2003045200A (ja) * 2001-08-02 2003-02-14 Mitsubishi Electric Corp 半導体モジュールおよびそれに用いる半導体記憶装置
DE10146149B4 (de) * 2001-09-19 2004-04-29 Infineon Technologies Ag Schaltungsanordnung zum Empfang eines Datensignals
KR100403635B1 (ko) * 2001-11-06 2003-10-30 삼성전자주식회사 동기식 반도체 메모리 장치의 데이터 입력 회로 및 데이터입력 방법
JP3657234B2 (ja) * 2002-03-08 2005-06-08 Ｎｅｃマイクロシステム株式会社 非同期インタフェース装置及び非同期インタフェース方法
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US6995554B2 (en) * 2004-06-16 2006-02-07 Agilent Technologies, Inc. Delay-locked loop and a method of testing a delay-locked loop
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KR100812600B1 (ko) * 2005-09-29 2008-03-13 주식회사 하이닉스반도체 주파수가 다른 복수의 클럭을 사용하는 반도체메모리소자
CN100527267C (zh) * 2006-02-28 2009-08-12 中国科学院计算技术研究所 Ddr和ddr2内存控制器的读数据采样方法及装置
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JP5687412B2 (ja) 2009-01-16 2015-03-18 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びそのリード待ち時間調整方法、メモリシステム、並びに半導体装置
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KR100991308B1 (ko) 2008-05-20 2010-11-01 주식회사 하이닉스반도체 불휘발성 메모리 소자 및 그 테스트 방법
US7881127B2 (en) 2008-05-20 2011-02-01 Hynix Semiconductor Inc. Nonvolatile memory device and method of testing the same

Also Published As

Publication number Publication date
KR20000005666A (ko) 2000-01-25
US6324118B1 (en) 2001-11-27
US20010015927A1 (en) 2001-08-23
US6330200B2 (en) 2001-12-11
US20020039315A1 (en) 2002-04-04
US6522598B2 (en) 2003-02-18
JP2000076853A (ja) 2000-03-14

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