IT1251047B - Metodo per la formazione di interconnessione multilivello in un dispositivo a semiconduttore - Google Patents

Metodo per la formazione di interconnessione multilivello in un dispositivo a semiconduttore

Info

Publication number
IT1251047B
IT1251047B ITMI912187A ITMI912187A IT1251047B IT 1251047 B IT1251047 B IT 1251047B IT MI912187 A ITMI912187 A IT MI912187A IT MI912187 A ITMI912187 A IT MI912187A IT 1251047 B IT1251047 B IT 1251047B
Authority
IT
Italy
Prior art keywords
dielectric layer
layer
hole
semiconductor device
formation
Prior art date
Application number
ITMI912187A
Other languages
English (en)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI912187A0 publication Critical patent/ITMI912187A0/it
Publication of ITMI912187A1 publication Critical patent/ITMI912187A1/it
Application granted granted Critical
Publication of IT1251047B publication Critical patent/IT1251047B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Interconnessione multilivello di un dispositivo a semiconduttore per formare un foro via su un elettrodo di primo strato, quindi per formare un elettrodo di secondo strato, che comprende gli stadi di:formazione di un primo strato dielettrico sull'intera superficie del substrato semiconduttore dove è stato formato l'elettrodo di primo strato;riempimento della rientranza mediante formazione di materiale isolante su detto primo strato dielettrico;laminazione del secondo strato dielettrico su detto primo strato dielettrico e su detto materiale isolante;formazione di detto foro via mediante esecuzione di un processo fotolitografico su detto secondo strato dielettrico formato su detto primo strato dielettrico;formazione di uno strato isolante sull'intera superficie del substrato semiconduttore dove è stato formato detto foro via;formazione di uno spaziatore sulla parete laterale del foro via mediante attacco anisotropo di detto strato isolante;deposizione di materiale conduttivo all'interno di detto foro via, la cui parete laterale è formata dallo spaziatore e dall'intera superficie di detto secondo strato dielettrico.
ITMI912187A 1991-01-14 1991-08-02 Metodo per la formazione di interconnessione multilivello in un dispositivo a semiconduttore IT1251047B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000450A KR920015542A (ko) 1991-01-14 1991-01-14 반도체장치의 다층배선형성법

Publications (3)

Publication Number Publication Date
ITMI912187A0 ITMI912187A0 (it) 1991-08-02
ITMI912187A1 ITMI912187A1 (it) 1993-02-02
IT1251047B true IT1251047B (it) 1995-05-02

Family

ID=19309729

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI912187A IT1251047B (it) 1991-01-14 1991-08-02 Metodo per la formazione di interconnessione multilivello in un dispositivo a semiconduttore

Country Status (6)

Country Link
US (1) US5219792A (it)
KR (1) KR920015542A (it)
DE (1) DE4125221A1 (it)
FR (1) FR2671664B1 (it)
GB (1) GB2251722B (it)
IT (1) IT1251047B (it)

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KR960006693B1 (ko) * 1992-11-24 1996-05-22 현대전자산업주식회사 고집적 반도체 접속장치 및 그 제조방법
US5502006A (en) * 1993-11-02 1996-03-26 Nippon Steel Corporation Method for forming electrical contacts in a semiconductor device
US5395785A (en) * 1993-12-17 1995-03-07 Sgs-Thomson Microelectronics, Inc. SRAM cell fabrication with interlevel dielectric planarization
US5453406A (en) * 1994-06-13 1995-09-26 Industrial Technology Research Institute Aspect ratio independent coating for semiconductor planarization using SOG
US5643407A (en) * 1994-09-30 1997-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Solving the poison via problem by adding N2 plasma treatment after via etching
US5795208A (en) * 1994-10-11 1998-08-18 Yamaha Corporation Manufacture of electron emitter by replica technique
US5599749A (en) * 1994-10-21 1997-02-04 Yamaha Corporation Manufacture of micro electron emitter
US5459086A (en) * 1994-11-07 1995-10-17 United Microelectronics Corporation Metal via sidewall tilt angle implant for SOG
KR0138295B1 (ko) * 1994-11-30 1998-06-01 김광호 도전선 형성방법
JP3369817B2 (ja) * 1995-06-23 2003-01-20 三菱電機株式会社 半導体装置
KR0171733B1 (ko) * 1995-08-28 1999-03-30 김주용 반도체 소자의 콘택홀 형성 방법
JPH10509285A (ja) * 1995-09-14 1998-09-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 縮小したフィーチャーサイズのためのダマスクプロセス
US5640038A (en) * 1995-11-22 1997-06-17 Vlsi Technology, Inc. Integrated circuit structure with self-planarized layers
KR100214467B1 (ko) * 1995-12-29 1999-08-02 구본준 반도체소자의 배선구조 형성방법
US5597764A (en) * 1996-07-15 1997-01-28 Vanguard International Semiconductor Corporation Method of contact formation and planarization for semiconductor processes
DE69728852D1 (de) * 1997-01-31 2004-06-03 St Microelectronics Srl Verfahren zur Herstellung von einer morphologischen Randstruktur um ein integriertes elektronisches Bauelement zu versiegeln, sowie ein entsprechendes Bauelement
US5863707A (en) * 1997-02-11 1999-01-26 Advanced Micro Devices, Inc. Method for producing ultra-fine interconnection features
SG80582A1 (en) * 1997-03-20 2001-05-22 Chartered Semiconductor Mfg Use of an insulator spacer on the sidewalls of a via hole
US5913150A (en) * 1997-04-11 1999-06-15 Nec Corporation Method for manufacturing semiconductor device using spin on glass layer
US5759906A (en) * 1997-04-11 1998-06-02 Industrial Technology Research Institute Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US6309956B1 (en) 1997-09-30 2001-10-30 Intel Corporation Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
US6255232B1 (en) * 1999-02-11 2001-07-03 Taiwan Semiconductor Manufacturing Company Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer
US6207554B1 (en) * 1999-07-12 2001-03-27 Chartered Semiconductor Manufacturing Ltd. Gap filling process in integrated circuits using low dielectric constant materials
JP2001077086A (ja) 1999-08-31 2001-03-23 Oki Electric Ind Co Ltd 半導体装置のドライエッチング方法
JP3485504B2 (ja) 1999-09-09 2004-01-13 沖電気工業株式会社 半導体装置のドライエッチング方法
KR100389034B1 (ko) * 2000-11-30 2003-06-25 삼성전자주식회사 반도체 장치의 상하층 접속 형성 방법 및 그 방법에 의해형성된 반도체 장치
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US20080172080A1 (en) * 2007-01-16 2008-07-17 Isham John Minimally invasive rectal balloon apparatus
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JPH0763064B2 (ja) * 1986-03-31 1995-07-05 株式会社日立製作所 Ｉｃ素子における配線接続方法
GB2206729B (en) * 1987-07-01 1990-10-24 British Aerospace A method of forming electrical contacts in a multi-level interconnect system
US4977105A (en) * 1988-03-15 1990-12-11 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing interconnection structure in semiconductor device
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US5068711A (en) * 1989-03-20 1991-11-26 Fujitsu Limited Semiconductor device having a planarized surface
KR910013463A (ko) * 1989-12-29 1991-08-08 김광호 반도체 소자의 개구형성방법
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Also Published As

Publication number Publication date
US5219792A (en) 1993-06-15
GB2251722A (en) 1992-07-15
DE4125221A1 (de) 1992-07-16
DE4125221C2 (it) 1993-07-22
ITMI912187A0 (it) 1991-08-02
KR920015542A (ko) 1992-08-27
GB9116831D0 (en) 1991-09-18
GB2251722B (en) 1995-01-04
ITMI912187A1 (it) 1993-02-02
FR2671664B1 (fr) 2004-08-27
FR2671664A1 (fr) 1992-07-17

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970828