GB2206729B - A method of forming electrical contacts in a multi-level interconnect system - Google Patents

A method of forming electrical contacts in a multi-level interconnect system

Info

Publication number
GB2206729B
GB2206729B GB8715486A GB8715486A GB2206729B GB 2206729 B GB2206729 B GB 2206729B GB 8715486 A GB8715486 A GB 8715486A GB 8715486 A GB8715486 A GB 8715486A GB 2206729 B GB2206729 B GB 2206729B
Authority
GB
United Kingdom
Prior art keywords
electrical contacts
interconnect system
level interconnect
forming electrical
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB8715486A
Other versions
GB2206729A (en
GB8715486D0 (en
Inventor
Alan Peter Pritchard
Stephen Paul Lake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems PLC
Original Assignee
British Aerospace PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Aerospace PLC filed Critical British Aerospace PLC
Priority to GB8715486A priority Critical patent/GB2206729B/en
Publication of GB8715486D0 publication Critical patent/GB8715486D0/en
Publication of GB2206729A publication Critical patent/GB2206729A/en
Application granted granted Critical
Publication of GB2206729B publication Critical patent/GB2206729B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB8715486A 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system Expired - Lifetime GB2206729B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8715486A GB2206729B (en) 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8715486A GB2206729B (en) 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system

Publications (3)

Publication Number Publication Date
GB8715486D0 GB8715486D0 (en) 1987-08-05
GB2206729A GB2206729A (en) 1989-01-11
GB2206729B true GB2206729B (en) 1990-10-24

Family

ID=10619909

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8715486A Expired - Lifetime GB2206729B (en) 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system

Country Status (1)

Country Link
GB (1) GB2206729B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910013463A (en) * 1989-12-29 1991-08-08 김광호 Opening Method of Semiconductor Device
KR920015542A (en) * 1991-01-14 1992-08-27 김광호 Multi-layered wiring formation method of semiconductor device
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1326758A (en) * 1969-11-07 1973-08-15 Ibm Integrated semiconductor structure
GB2150749A (en) * 1983-12-03 1985-07-03 Standard Telephones Cables Ltd Integrated circuits
GB2156593A (en) * 1984-03-28 1985-10-09 Plessey Co Plc Through hole interconnections
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1326758A (en) * 1969-11-07 1973-08-15 Ibm Integrated semiconductor structure
GB2150749A (en) * 1983-12-03 1985-07-03 Standard Telephones Cables Ltd Integrated circuits
GB2156593A (en) * 1984-03-28 1985-10-09 Plessey Co Plc Through hole interconnections
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit

Also Published As

Publication number Publication date
GB2206729A (en) 1989-01-11
GB8715486D0 (en) 1987-08-05

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930701