GB2206729A - Integrated circuit multi-level interconnect system - Google Patents

Integrated circuit multi-level interconnect system Download PDF

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Publication number
GB2206729A
GB2206729A GB8715486A GB8715486A GB2206729A GB 2206729 A GB2206729 A GB 2206729A GB 8715486 A GB8715486 A GB 8715486A GB 8715486 A GB8715486 A GB 8715486A GB 2206729 A GB2206729 A GB 2206729A
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GB
United Kingdom
Prior art keywords
aperture
electrically conductive
bridging
polyimide
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8715486A
Other versions
GB8715486D0 (en
GB2206729B (en
Inventor
Alan Peter Pritchard
Stephen Paul Lake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems PLC
Original Assignee
British Aerospace PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Aerospace PLC filed Critical British Aerospace PLC
Priority to GB8715486A priority Critical patent/GB2206729B/en
Publication of GB8715486D0 publication Critical patent/GB8715486D0/en
Publication of GB2206729A publication Critical patent/GB2206729A/en
Application granted granted Critical
Publication of GB2206729B publication Critical patent/GB2206729B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of fabricating multi-level interconnect systems comprising metal contact portions (42, 10) with polyimide insulating layers (12) sandwiched therebetween involving spinning a polyimide filling layer over apertures formed in the polyimide insulating layer so that polyimide fillets (40) accumulate in any cracks in the bases of the apertures before metal contact portion (42) is provided. <IMAGE>

Description

FORs!IliG ELECERICAL CONTACTS The present invention relates to forming electrical contacts especially in the context of fabricatins a multi-level interconnect system fondling part of an integrated circuit.
In known nethods of fabricating integrated circuits involving multi-level interconnect systems a dielectric layer eg. polyimide is deposited on a metal layer, eg. aluminium, forming the normal top la,ver of an integrated circuit wafer. Through holes are formed to enable inter level connections and metal is deposited in an appropriate configuration so as to make the desired connections. The preceding steps are then repeated as required to build up a multi-level structure of the type shown schematically in Figure A. In Figure A a base layer 10 of aluminium has deposited thereon a layer 12 of polyimide in which are formed apertures 14 and 16 and a further polyimide layer 18 formed with an aperture 20.Aluminium contact portions 22, 24 and 26 are disposed in the apertures 14, 16 and 20 respectively to enable interlevel connections to be made.
A problem with existing interlevel interconnect systems is that thick polyimide layers can be highly stressed and liable to crack at the bottoms of the apertures thus making subsequent metal step coverage very unreliable. Cracking is especially likely when there is a polymer/metal interface in view of the very different thermal characteristics of these materials. In Figure B cracking is illustrated at the base 28 of the aperture 14 and, in practice, the electrical contact portion 22 may not properly bridge the gap formed by the crack in the polyimide around the base 28 of the aperture 14.
According to t'ne present invention we provide a method of forming electrical contacts between levels in a multi-layer interconnect ss,)ster.l in which electrically conductive portions are separated by a dielectric i.atrial, comprising:- forming an aperture in the dielectric material; depositing a substance in the aperture to bridge any cracks in the surface defining the aperture; etching the bridging material so as to expose an underlying electrically conductive portion; depositing an electrically conductive portion on the dielectric material so that it enters the aperture and makes electrical contact with said underlying electrically conductive portion.
The bridging material forms a fillet in the crack region as a result of surface tension and spinning conditions thereby enabling reliable electrical connections to be formed.
Preferably, the bridging material is also a dielectric and, in the embodiment to be described, the bridging material and the dielectric layer are both formed from polyimide.
Optionally, the method may comprise depositing electrically conductive material in the aperture prior to depositing the bridging material, and depositing an extra portion of electrically conductive material on the bridging material after said etching step.
The second embodiment to be described relates to the optional method in which the crack region is shunted with a further electrically conductive portion deposited on top of a polyimide bridging layer which accumulates a fillet in the crack region.
According to another aspect of the present invention we provide a multi-level interconnect system comprising at least two portions of electrically conductive material separated by a dielectric layer and comprising apertures in the dielectric layer to permit electrical contact between levels wherein the apertures contain fillets of material for bridging cracks in the surfaces defining the apertures.
Preferred embodiments of the present invention may now be described, by way of example, with reference to the accompanying drawings in which: Figures 1 - 4 are diagrams showing stages in a method according to the present invention; Figures 5 - 7 are diayrams showing stages in a second embodiment of a method according to the present invention.
Figure 1 shows a polyimide insulating layer 12 deposited on an aluminium base layer 10. An aperture 30 is formed in the polyimide layer 12 and a polyimide bridging layer 32 has been spun over the aperture 30 so that it accumulates in t'ne base of the aperture 30 which includes a cracked region 34. A metal mask 36 is then applied, as shown in Figure 2. The aperture 38 in the mask 36 is appreciably larger than the mouth of the aperture 30 in the polyimide layer 12. A polyimide etch is performed resulting in the configuration shown in Figure 3 where portions of the side walls of the aperture 30 have been removed and a fillet 40 of polyimide remains in the base of the aperture 30 bridging the cracked region 34. The mask 36 is then removed and an aluminiun portion 42 is deposited to make reliable electrical contact with the base layer 10.
An alternative embodiment is shown in Figures 5 - 7 in which an aluminium contact portion 44 is deposited in an aperture 46 in the polyimide layer 12 despite a cracked region 48 at the base of the aperture 46. A bridging layer 50 of polyimide is then spun over the aperture 46 as shown in Figure 5. A mask is applied (not shown) and a polyimide etch performed to produce the stage shown in Figure 6 in which a fillet 52 of polyimide bridges the cracked region 48 inside the aperture 46. A further aluminium contact portion 54 is applied and contacts the aluminium layer 44 at the bottom of the aperture 46, as shown in Figure 7, to establish reliable electrical contact.
The method of the present invention enables multi-level interconnect systems to be fabricated with much greater reliability than before.

Claims (8)

  1. cTTM
    CLA 1. The method of forming electrical contacts between levels in a multi-level interconnect system in which electrically conductive portions are separated by a dielectric material, comprising:- forming an aperture in the dielectric material; depositing a substance in the aperture to bridge any cracks in the surface defining the aperture; etching the bridging material so as to expose an underlying electrically conductive portion; depositing an electrically conductive portion on the dielectric material so that it enters the aperture and makes electrical contact with the underlying electrically conductive portion.
  2. 2. A method according to claim 1 wherein the bridging material is electrically insulative material.
  3. 3. A method according to claim 2 wherein the bridging material is the same as the dielectric material and wherein, prior to said etching step, a mask is used to define the aperture.
  4. 4. A method according the claim 3 wherein the bridging material and the dielectric material are both polyimide.
  5. 5. A method according to any preceding claim comprising depositing electrically conductive material in the aperture prior to depositing the bridging material, and depositing an extra portion of electrically conductive material on the bridging material after said etching step.
  6. 6. A method substantially as herein described with reference to, and as illustrated in, Figures 1-4 or Figures 5-8 of the accompanying drawings.
  7. 7. A multi-level interconnect system comprising at least two portions of electrically conductive material separated by a dielectric layer and comprising apertures in the dielectric layer to permit electrical contact between levels wherein the apertures contain fillets of material for bridging cracks in the surfaces defining the apertures.
  8. 8. A multi-level interconnect system substances herein described with reference to, and as illustrated in, Figures 1 - 4 or Figures 5 8 of the accompanying drawings.
GB8715486A 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system Expired - Lifetime GB2206729B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8715486A GB2206729B (en) 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8715486A GB2206729B (en) 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system

Publications (3)

Publication Number Publication Date
GB8715486D0 GB8715486D0 (en) 1987-08-05
GB2206729A true GB2206729A (en) 1989-01-11
GB2206729B GB2206729B (en) 1990-10-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB8715486A Expired - Lifetime GB2206729B (en) 1987-07-01 1987-07-01 A method of forming electrical contacts in a multi-level interconnect system

Country Status (1)

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GB (1) GB2206729B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2239559A (en) * 1989-12-29 1991-07-03 Samsung Electronics Co Ltd Forming connections in semiconductor devices
GB2251722A (en) * 1991-01-14 1992-07-15 Samsung Electronics Co Ltd Method for forming multilevel interconnection in a semiconductor device
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1326758A (en) * 1969-11-07 1973-08-15 Ibm Integrated semiconductor structure
GB2150749A (en) * 1983-12-03 1985-07-03 Standard Telephones Cables Ltd Integrated circuits
GB2156593A (en) * 1984-03-28 1985-10-09 Plessey Co Plc Through hole interconnections
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1326758A (en) * 1969-11-07 1973-08-15 Ibm Integrated semiconductor structure
GB2150749A (en) * 1983-12-03 1985-07-03 Standard Telephones Cables Ltd Integrated circuits
GB2156593A (en) * 1984-03-28 1985-10-09 Plessey Co Plc Through hole interconnections
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2239559A (en) * 1989-12-29 1991-07-03 Samsung Electronics Co Ltd Forming connections in semiconductor devices
GB2251722A (en) * 1991-01-14 1992-07-15 Samsung Electronics Co Ltd Method for forming multilevel interconnection in a semiconductor device
GB2251722B (en) * 1991-01-14 1995-01-04 Samsung Electronics Co Ltd Method for forming multilevel interconnection in a semiconductor device
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
US6033980A (en) * 1995-12-19 2000-03-07 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit

Also Published As

Publication number Publication date
GB8715486D0 (en) 1987-08-05
GB2206729B (en) 1990-10-24

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930701