JPS63221645A - Method for connection between wirings in semiconductor device - Google Patents
Method for connection between wirings in semiconductor deviceInfo
- Publication number
- JPS63221645A JPS63221645A JP5593987A JP5593987A JPS63221645A JP S63221645 A JPS63221645 A JP S63221645A JP 5593987 A JP5593987 A JP 5593987A JP 5593987 A JP5593987 A JP 5593987A JP S63221645 A JPS63221645 A JP S63221645A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- hole
- film
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims description 20
- 239000012212 insulator Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000000059 patterning Methods 0.000 abstract description 6
- 238000000926 separation method Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は半導体装置の配線間接続方法に関するもので
、特に、多層構造の配線間接続方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for connecting wires in a semiconductor device, and particularly to a method for connecting wires in a multilayer structure.
[従来の技#]
第2図に従来の半導体装置の多層構造の配線間接続方法
の一例を示す。[Conventional Technique #] FIG. 2 shows an example of a conventional method for connecting interconnects in a multilayer structure of a semiconductor device.
図において、1は基板、2は第1分離絶縁膜。In the figure, 1 is a substrate, and 2 is a first isolation insulating film.
3は第1配線、5はスルーホール部、7は第2分離絶縁
膜、8は第2配線である。3 is a first wiring, 5 is a through hole portion, 7 is a second isolation insulating film, and 8 is a second wiring.
次に配線間接続方法について説明する。第2図(a )
に示すように基板1上に第1分離絶縁[12を形成後、
第1配線層を形成し、所定のパターニングを行ない、第
1配線3を形成する。次に第2図(b ) 1.:示f
ヨ’5に:、11 配[113ト第1分m1e縁112
上に第2分雌部1311I7を形成後、第1配線3上の
第2分離絶縁膜7の一部を除去し、スルーホール部5を
形成する。さらに、スルーホール部5と第2分離絶縁膜
7上に第2配線層を形成後、所定のバターニングを行な
い、第2配線8を形成する。Next, a method for connecting wires will be explained. Figure 2 (a)
After forming the first isolation insulation [12] on the substrate 1 as shown in FIG.
A first wiring layer is formed and predetermined patterning is performed to form the first wiring 3. Next, Figure 2(b) 1. :show f
Yo'5:, 11 arrangement [113 to 1st minute m1e edge 112
After forming the second female part 1311I7 thereon, a part of the second isolation insulating film 7 on the first wiring 3 is removed to form a through hole part 5. Further, after forming a second wiring layer on the through hole portion 5 and the second isolation insulating film 7, a predetermined patterning is performed to form a second wiring 8.
[発明が解決しようとする問題点]
従来の配線間接続方法では、第2分離絶縁117と第2
配線8が同様な膜厚たとえば8000A〜10000A
程度と厚く、スルーホール部5の段差での第2配線8の
カバレッジが悪くなり、第2配線8の断線を引き起こす
という欠点があった。[Problems to be Solved by the Invention] In the conventional interconnection connection method, the second separation insulator 117 and the second
The wiring 8 has a similar film thickness, for example, 8000A to 10000A.
This has the disadvantage that the coverage of the second wiring 8 at the step of the through-hole portion 5 is poor, causing the second wiring 8 to be disconnected.
本発明は、上記の欠点を除去するためになされたもので
、スルーホール部5の絶縁膜との段差を° なくし、
第2配線8のカバレッジ不良から発生する断線を防止で
きる配線閤節即構造を得ることを目的とする。The present invention has been made to eliminate the above-mentioned drawbacks, and eliminates the level difference between the through-hole portion 5 and the insulating film.
It is an object of the present invention to obtain a wiring fastening structure that can prevent wire breakage caused by poor coverage of the second wiring 8.
[問題点を解決するための手段]
この発明における配線間接続方法は第1配線と第2配線
の接続を一定厚さを有するスルーホール配線膜を介して
行なうようにしたものである。[Means for Solving the Problems] The interconnection connection method according to the present invention connects a first interconnection and a second interconnection through a through-hole interconnection film having a constant thickness.
[作用]
この発明における配線間接続方法によれば、第1配線と
第2配線の接続は、一定膜厚を有するスルーホール配線
膜によって行なわれるため、従来生じていた接続部での
段差が解消できる。[Function] According to the wiring connection method of the present invention, the first wiring and the second wiring are connected by a through-hole wiring film having a constant film thickness, so that the level difference at the connection part that conventionally occurs can be eliminated. can.
[発明の実施例]
以下、この発明の一実施例を図について説明する。第1
図において1は半導体基板、2は第1分離絶縁膜、3は
第1配線、4はスルーホール配線躾形成用絶縁躾、5は
スルーホール部、6はスルーホール配線膜、7は第2分
離絶縁膜、8は第2配線を示す。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, 1 is a semiconductor substrate, 2 is a first isolation insulating film, 3 is a first wiring, 4 is an insulating film for through-hole wiring formation, 5 is a through-hole part, 6 is a through-hole wiring film, and 7 is a second isolation film. The insulating film 8 indicates the second wiring.
第1図(a)に示すように、半導体基板1上に、第1分
離絶縁膜2を形成後、第1配線層を形成し、所定のバタ
ーニングを行ない、第1配線3を形成する。さらに、第
1分離絶縁膜2および第1配線3上に、スルーホール配
IIIIl形成用絶縁lI4を形成し、第1配線上の一
部を除去しスルーホール部を形成後、スルーホール5l
s5とスルーホール配線膜形成用絶縁114上にスルー
ホール配線116を形成する。次に第1図(b)に示す
ように、スルーホール部5とその外側の一部を残してス
ルーホール配線躾のスルーホール配線1lI6の一部を
除去し、スルーホール配線116を形成する。次に第1
図(C)のように、スルーホール配線膜6とスルーホー
ル配線膜形成用絶縁114上に第2分離絶縁膜7を、ス
ルーホール配線116の段差が埋まる程度の膜厚に形成
する。次に第1v!A(d)に示すように、第2分離絶
縁膜7をたとえばエッチバック法で、スルーホール配線
膜6の表面まで除去する。As shown in FIG. 1(a), after forming a first isolation insulating film 2 on a semiconductor substrate 1, a first wiring layer is formed and a predetermined patterning is performed to form a first wiring 3. Furthermore, an insulator lI4 for through-hole wiring IIIl formation is formed on the first isolation insulating film 2 and the first wiring 3, and after removing a portion on the first wiring to form a through-hole portion, the through-hole 5l is formed.
A through-hole wiring 116 is formed on s5 and the insulator 114 for through-hole wiring film formation. Next, as shown in FIG. 1(b), a part of the through-hole wiring 1lI6 of the through-hole wiring is removed, leaving the through-hole portion 5 and a portion outside thereof, to form a through-hole wiring 116. Then the first
As shown in FIG. 3C, a second isolation insulating film 7 is formed on the through-hole wiring film 6 and the through-hole wiring film-forming insulator 114 to a thickness that is sufficient to fill the step of the through-hole wiring 116. Next is the 1st v! As shown in A(d), the second isolation insulating film 7 is removed down to the surface of the through-hole wiring film 6 by, for example, an etch-back method.
次に第1図(e )に示すように、第2分離絶縁膜7と
、スルーホール配線膜6上に第2配amを形成後、所定
のバターニングを行ない、第2配線8を形成し、第1配
線3と第2配線8をスルーホール配線116を介して接
続する。Next, as shown in FIG. 1(e), after forming a second wiring pattern on the second isolation insulating film 7 and the through-hole wiring film 6, a predetermined patterning process is performed to form a second wiring 8. , the first wiring 3 and the second wiring 8 are connected via a through-hole wiring 116.
なお上記実施例では、半導体基板上に形成した例で述べ
たが、半導体基板以外の導体または絶縁物基板であって
もよい。また第1分離絶縁膜、第1配線、第2分離絶縁
膜、第2配線で構成される2層構造について述べたが、
それ以上の複数層構造であってもよい。In the above embodiments, an example was described in which the semiconductor substrate was formed on a semiconductor substrate, but a conductor or insulator substrate other than the semiconductor substrate may be used. Furthermore, although the two-layer structure consisting of the first isolation insulating film, the first wiring, the second isolation insulating film, and the second wiring has been described,
It may also have a multi-layered structure.
[発明の効果]
以上のようにこの発明によれば、第1配線と第2配縮と
のスルーホール部での配線接続をスルーホール部に一定
厚さのスルーホール配線膜を形成することによって行な
うようにしたので、接続部での段差がなくなり、断線の
発生を防止できるため、信頼性の高い配線接続を行なう
ことができる。[Effects of the Invention] As described above, according to the present invention, the wiring connection between the first wiring and the second wiring at the through-hole portion is achieved by forming a through-hole wiring film of a constant thickness in the through-hole portion. By doing so, there is no difference in level at the connection portion, and the occurrence of wire breakage can be prevented, so that highly reliable wiring connections can be made.
また信頼性の高いデバイスな冑ることができる。It can also be a reliable device.
第1図に本発明による配線接続方法を、また第2図には
従来の方法による配線接続方法を示す。
図において1は基板、2は第1分離絶縁膜、3は第1配
線、4はスルーホール配I!A膜形成用絶縁躾、5はス
ルーホール部、6はスルーホール配sum。
7は第2分離絶縁膜、8は第2配線である。
なお、図中同一符号は同一、または相当部分を示す。FIG. 1 shows a wiring connection method according to the present invention, and FIG. 2 shows a wiring connection method according to a conventional method. In the figure, 1 is a substrate, 2 is a first isolation insulating film, 3 is a first wiring, and 4 is a through hole wiring I! A is an insulating layer for film formation, 5 is a through-hole portion, and 6 is a through-hole arrangement sum. 7 is a second isolation insulating film, and 8 is a second wiring. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (3)
を形成し、前記第1分離絶縁膜上に第1配線を形成し、
前記第1配線の上にスルーホール配線膜形成用絶縁膜を
形成し、前記スルーホール配線膜形成用絶縁膜の一部を
除去して前記第1配線に至るスルーホールを形成後、前
記スルーホールを貫通して前記第1配線と接触し、所定
の厚さのスルーホール配線膜を形成し、前記スルーホー
ル配線膜の上表面を露出した状態で前記スルーホール配
線膜形成用絶縁膜上に第2分離絶縁膜を形成し、前記ス
ルーホール配線膜の露出部に接触し、前記第2分離絶縁
膜上に第2配線膜を形成することを特徴とする半導体装
置の配線間接続方法。(1) preparing a semiconductor substrate, forming a first isolation insulating film on the substrate, and forming a first wiring on the first isolation insulating film;
After forming an insulating film for forming a through-hole wiring film on the first wiring and removing a part of the insulating film for forming a through-hole wiring film to form a through hole leading to the first wiring, the through-hole a through-hole wiring film of a predetermined thickness is formed by penetrating through the through-hole wiring film into contact with the first wiring, and with the upper surface of the through-hole wiring film exposed, the first through-hole wiring film is formed on the insulating film for forming the through-hole wiring film. 1. A method for connecting interconnects in a semiconductor device, comprising forming a second isolation insulating film, contacting an exposed portion of the through-hole wiring film, and forming a second interconnect film on the second isolation insulating film.
縁物基板としたことを特徴とする特許請求の範囲第1項
記載の配線間接続方法。(2) The interconnection connection method according to claim 1, wherein the semiconductor substrate is a conductor or insulator substrate other than a semiconductor substrate.
たことを特徴とする特許請求の範囲第1項記載の配線間
接続方法。(3) The interconnection connection method according to claim 1, wherein the interconnection film has a multilayer structure of three or more layers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5593987A JPS63221645A (en) | 1987-03-10 | 1987-03-10 | Method for connection between wirings in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5593987A JPS63221645A (en) | 1987-03-10 | 1987-03-10 | Method for connection between wirings in semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63221645A true JPS63221645A (en) | 1988-09-14 |
Family
ID=13013044
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5593987A Pending JPS63221645A (en) | 1987-03-10 | 1987-03-10 | Method for connection between wirings in semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63221645A (en) |
-
1987
- 1987-03-10 JP JP5593987A patent/JPS63221645A/en active Pending
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