GB2239559A - Forming connections in semiconductor devices - Google Patents

Forming connections in semiconductor devices Download PDF

Info

Publication number
GB2239559A
GB2239559A GB9013153A GB9013153A GB2239559A GB 2239559 A GB2239559 A GB 2239559A GB 9013153 A GB9013153 A GB 9013153A GB 9013153 A GB9013153 A GB 9013153A GB 2239559 A GB2239559 A GB 2239559A
Authority
GB
United Kingdom
Prior art keywords
insulating layer
opening
conductor
substrate
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9013153A
Other versions
GB9013153D0 (en
Inventor
Kyungseok Oh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB9013153D0 publication Critical patent/GB9013153D0/en
Publication of GB2239559A publication Critical patent/GB2239559A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H01L23/4855—Overhang structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of manufacturing a semiconductor device is described in which a spacer (18') is provided in an opening (19) and between a first conductor (12) and a further conductor (20) so as to fix a certain gap between the two conductors. The spacer (18') results from the selective etching of a third insulating layer provided before the further conductor is applied. The size of the gap between the first and further conductors is not reliant upon the accuracy of the position of an etching mask upon the device. Moreover, a "step-coverage problem" is alleviated by a gently sloping entrance to the opening. <IMAGE>

Description

A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE The present invention
relates to a method of manufacturing a semiconductor device. The method is especially useful for forming an opening for use in carrying out inter-layer connections, ion implantations or ion diffusions on a semiconductor substrate.
Figures 1A and 1B illustrate a method of forming an opening according to a conventional technique. Referring to Figure 1A, a semiconductor substrate 1 is provided with an electrically insulating layer 3 and a first electrical conductor 2. Photo-resist 4 is deposited on the insulating layer 3 except for an opening 5. Then, as shown in Figure 1B. the region of the insulating layer 3 lying below the opening 5 is etched down to the surface of the semiconductor substrate 1, forming a trench 6. Subsequently, the photo-resist is removed and a second electrical conductor 7 is applied.
If. during the opening-forming method according to the conventional technique, a misalignment occurs between the positions of the opening 5 and the semiconductor structure (items 1 to 3) then, on one side of the trench 6, the gap 8 between the f irst and second conductors 2,7 is reduced so that a short circuit may be formed between the first and second conductors 2,7, thereby causing the flow of leakage currents.
Furthermore, with the second conductor 7.applied on to the inside of the trench 6, there is a 91step coverage problem" in that the step at the enCrance of the trench 6 is enlarged, thereby aggravating coverage of the step of the second conductor 7. Also, there is a limit to reducing the size of the semiconductor device because there is a limit to reducing the width of the gap between the trench 6 and the first conductor 2.
According to the present invention from one aspect, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
providing one after the other on a substrate a first insulating layer, a first conductor, a second insulating layer and photo-resist, the latter leaving a first opening; etching through said insulating layers and said first conductor to said substrate using said photoresist as a mask, thus forming a second opening; removing said photo-resist; applying a third insulating layer; - selectively etching said third insulating layer using an etch-back process so as to leave remaining on the inner wall of said second opening a region of the third insulating layer for serving as a spacer; and applying a further conductor on to said region to form a third opening.
According to the present invention from another aspect, there is provided a semiconductor device comprising:
substrate; first insulating layer, a first conductor and a second insulating layer one after the other on said substrate; a first opening. which extends through said layers and said conductor to said substrate; a third insulating layer on the inner wall. of said first opening for serving as a spacer; and a further conductor on said third insulating layer and providing a second opening.
The present invention will. now be described, by way of examplei with reference to the accompanying drawings, in which:
Figures 1A and 1B are sectional views illustrating formation of a device using a conventional method; and Figures 2A and 2B are sectional views illustrating formation of a device using a method according to an example of the present invention.
Referring to Figure 2A, a first insulating layer 11, a first conductor 12, a second insulating layer 13 and another conductor 14 are deposited upon a semiconductor substrate 10 one after the other. Upon the other conductor 14. photo-resist 15 is deposited using a masking process except for a first opening 16.
Then, as shown in Figure 2B r the region of the device lying below the first opening 16 is etched down to the surface of the semiconductor substrate 10, forming a second opening 17. Subsequently, the photoresist 15 is removed, and a third insulating layer 18 is deposited.
Then. as shown in Figure 2C. the third insulating layer 18 is selectively etched using an etch-back process not involving the use of a mask so that a region of the third insulating layer 18 remains on the inner wall of the second opening 17. This remaining region forms a spacer 18'. Then a further conductor 20 is deposited, leaving a third opening 19.
j In the resulting device, shown in Figure 2C, the first conductor 12 and the further conductor 20 are separated from each other by the presence of the spacer 181, thus overcoming the possibility of a problem as described above due to misalignment between the positions of the opening 16 and the semiconductor structure (items 11 to 14).
Z Moreover, the "step-coverage problem", as described above, is substantially alleviated since, as shown in Figure 2C, no sharp corner exists at the entrance of the third opening 19 due to the gentle slope of the spacer 18'.
In the example of a method according to the present invention, the gaps between the conductors 12 and 20 are dependent upon the width of the spacer 18'. The sizes of the gaps can therefore be fixed easily and accurately.
Moreover. any further masking steps which might be necessary can be carried out more easily than for a device made using the conventional technique because the entrance to the opening 19 is relatively large, owing to the gentle slope of the spacer.

Claims (8)

CLAIKS
1. A method of manufacturing a semiconductor device, comprising the steps of: providing one after the other on a substrate a first insulating layer, a first conductor, a second insulating layer and photo-resist, the latter leaving a first opening; etching through said insulating layers and said first conductor to said substrate using said photo- resist as a mask, thus forming a second opening; removing said photo- resist; applying a third insulating layer; selectively etching said third insulating layer using an etch-back process so as to leave remaining on the inner wall of said second opening a region of the third insulating layer for serving as a spacer; and applying a further conductor on to said region to form a third opening.
2. A method according to Claim 1, wherein another conductor is provided after said second insulating layer, said photo- resist being provided on said other conductor and the latter also being etched through.
3. A method according to Claim 1 or 2 j wherein said substrate comprises a semiconductor substrate.
4. A semiconductor device comprising:
a substrate; a first insulating layer, a first conductor and a second insulating layer one af ter the other on said substrate; a first opening, which extends through said layers and said conductor to said substrate; a third insulating layer on the inner wall of said first opening for serving as a spacer; and a further conductor on said third insulating layer and providing a second opening.
5. A device according to Claim 4, wherein there is another conductor after said second insulating layer and through which said first opening extends.
6. A device according to Claim 4 or 5. wherein said substrate comprises a semiconductor substrate.
7. A method of manufacturing a semiconductor device, substantially as herein described with reference to Figures 2A. 2B and 2C of the accompanying drawings.
8. A semiconductor device, substantially as herein described with reference to Figure 2C of the accompanying drawings.
Published 1991 at Ile Patent Office. State House. 66171 HighHolborn. London WC1R4Tp. Further copies my be obtained from Sales Branch. Unit 6. Nine Mile Point. Cwrnfelinfach. Cross Keys. Newport- NP1 7HZ. Printed by Multiplex techniques lid. st Mary Cray. Kent.
GB9013153A 1989-12-29 1990-06-13 Forming connections in semiconductor devices Withdrawn GB2239559A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020099A KR910013463A (en) 1989-12-29 1989-12-29 Opening Method of Semiconductor Device

Publications (2)

Publication Number Publication Date
GB9013153D0 GB9013153D0 (en) 1990-08-01
GB2239559A true GB2239559A (en) 1991-07-03

Family

ID=19294139

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9013153A Withdrawn GB2239559A (en) 1989-12-29 1990-06-13 Forming connections in semiconductor devices

Country Status (4)

Country Link
JP (1) JPH03203323A (en)
KR (1) KR910013463A (en)
DE (1) DE4018437A1 (en)
GB (1) GB2239559A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2251722A (en) * 1991-01-14 1992-07-15 Samsung Electronics Co Ltd Method for forming multilevel interconnection in a semiconductor device
US5318925A (en) * 1992-07-03 1994-06-07 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a self-aligned interlayer contact in a semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4309611A1 (en) * 1993-03-24 1994-09-29 Siemens Ag Manufacturing process for a contact hole
DE4442652A1 (en) * 1994-11-30 1996-01-25 Siemens Ag Three=dimensional circuit metallisation plane contact hole formation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986001639A1 (en) * 1984-08-30 1986-03-13 American Telephone & Telegraph Company Electrical contact in semiconductor devices
GB2206729A (en) * 1987-07-01 1989-01-11 British Aerospace Integrated circuit multi-level interconnect system
GB2219434A (en) * 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010754A (en) * 1983-06-30 1985-01-19 Toshiba Corp Semiconductor device and manufacture thereof
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
JPS6278853A (en) * 1985-09-30 1987-04-11 Nec Corp Manufacture of semiconductor device
JPH0620101B2 (en) * 1986-09-29 1994-03-16 三菱電機株式会社 Semiconductor device
JP2666932B2 (en) * 1987-09-28 1997-10-22 株式会社東芝 Method for manufacturing semiconductor device
JPH01289142A (en) * 1988-05-16 1989-11-21 Nippon Telegr & Teleph Corp <Ntt> Vertical wiring structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986001639A1 (en) * 1984-08-30 1986-03-13 American Telephone & Telegraph Company Electrical contact in semiconductor devices
GB2206729A (en) * 1987-07-01 1989-01-11 British Aerospace Integrated circuit multi-level interconnect system
GB2219434A (en) * 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2251722A (en) * 1991-01-14 1992-07-15 Samsung Electronics Co Ltd Method for forming multilevel interconnection in a semiconductor device
GB2251722B (en) * 1991-01-14 1995-01-04 Samsung Electronics Co Ltd Method for forming multilevel interconnection in a semiconductor device
US5318925A (en) * 1992-07-03 1994-06-07 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a self-aligned interlayer contact in a semiconductor device

Also Published As

Publication number Publication date
JPH03203323A (en) 1991-09-05
GB9013153D0 (en) 1990-08-01
DE4018437A1 (en) 1991-07-11
KR910013463A (en) 1991-08-08

Similar Documents

Publication Publication Date Title
US6111319A (en) Method of forming submicron contacts and vias in an integrated circuit
KR960005870A (en) Metal wiring formation method of semiconductor device
GB2100926A (en) Field effect transistors
KR950011555B1 (en) Contact structure and manufacturing method thereof
US4174562A (en) Process for forming metallic ground grid for integrated circuits
GB2239559A (en) Forming connections in semiconductor devices
KR100237222B1 (en) Method for separating semiconductor device
US3974517A (en) Metallic ground grid for integrated circuits
KR970067640A (en) Method for forming a metal layer of a semiconductor
KR960019522A (en) Plug Formation Method for Semiconductor Devices
USH274H (en) Method of manufacturing an integrated circuit chip and integrated circuit chip produced thereby
KR0166488B1 (en) Fine contact forming method in the semiconductor device
KR0124638B1 (en) Manufacturing method of multilayer lining for semiconductor device
US4261096A (en) Process for forming metallic ground grid for integrated circuits
KR100333652B1 (en) A method for forming contact hole of semiconductor device
KR100306905B1 (en) Contact hole formation method
KR100396693B1 (en) method for forming metal line of semiconductor device
KR910000277B1 (en) Multilayer semiconductor
KR100248150B1 (en) Method of forming contact hole in semiconductor device
KR100232224B1 (en) Method of forming metal interconnector of semiconductor device
KR20000043099A (en) Method for forming conductive layer line of semiconductor device
KR100401535B1 (en) Method for manufacturing analog semiconductor device
KR100372657B1 (en) Method for forming contact of semiconductor device
KR100224778B1 (en) Fabrication method for semiconductor chip
KR0148611B1 (en) Formation method of element isolation layer for semiconductor devices

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)