KR910013463A - Opening Method of Semiconductor Device - Google Patents

Opening Method of Semiconductor Device Download PDF

Info

Publication number
KR910013463A
KR910013463A KR1019890020099A KR890020099A KR910013463A KR 910013463 A KR910013463 A KR 910013463A KR 1019890020099 A KR1019890020099 A KR 1019890020099A KR 890020099 A KR890020099 A KR 890020099A KR 910013463 A KR910013463 A KR 910013463A
Authority
KR
South Korea
Prior art keywords
semiconductor device
opening method
opening
forming
insulator
Prior art date
Application number
KR1019890020099A
Other languages
Korean (ko)
Inventor
오경석
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020099A priority Critical patent/KR910013463A/en
Priority to JP2050785A priority patent/JPH03203323A/en
Priority to DE4018437A priority patent/DE4018437A1/en
Priority to GB9013153A priority patent/GB2239559A/en
Publication of KR910013463A publication Critical patent/KR910013463A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H01L23/4855—Overhang structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

내용 없음.No content.

Description

반도체 소자의 개구형성방법Opening Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 제조공정도.2 is a manufacturing process diagram of the present invention.

Claims (1)

반도체 소자의 개구형성 방법에 있어서, 식각에 의해 반도체 기판상의 소정부분에 형성된 개구의 측벽에 부도체로 이루어진 스페이서(18')를 형성함을 특징으로 하는 반도체 소자의 개구형성 방법.A method for forming an opening in a semiconductor device, comprising: forming a spacer (18 ') made of an insulator on a sidewall of an opening formed in a predetermined portion on a semiconductor substrate by etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020099A 1989-12-29 1989-12-29 Opening Method of Semiconductor Device KR910013463A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019890020099A KR910013463A (en) 1989-12-29 1989-12-29 Opening Method of Semiconductor Device
JP2050785A JPH03203323A (en) 1989-12-29 1990-02-28 Manufacture of semiconductor device
DE4018437A DE4018437A1 (en) 1989-12-29 1990-06-08 METHOD FOR FORMING AN OPENING IN A SEMICONDUCTOR DEVICE
GB9013153A GB2239559A (en) 1989-12-29 1990-06-13 Forming connections in semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020099A KR910013463A (en) 1989-12-29 1989-12-29 Opening Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR910013463A true KR910013463A (en) 1991-08-08

Family

ID=19294139

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020099A KR910013463A (en) 1989-12-29 1989-12-29 Opening Method of Semiconductor Device

Country Status (4)

Country Link
JP (1) JPH03203323A (en)
KR (1) KR910013463A (en)
DE (1) DE4018437A1 (en)
GB (1) GB2239559A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920015542A (en) * 1991-01-14 1992-08-27 김광호 Multi-layered wiring formation method of semiconductor device
KR950011556B1 (en) * 1992-07-03 1995-10-06 현대전자산업주식회사 Ohmic contact forming method of semiconductor device
DE4309611A1 (en) * 1993-03-24 1994-09-29 Siemens Ag Manufacturing process for a contact hole
DE4442652A1 (en) * 1994-11-30 1996-01-25 Siemens Ag Three=dimensional circuit metallisation plane contact hole formation

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010754A (en) * 1983-06-30 1985-01-19 Toshiba Corp Semiconductor device and manufacture thereof
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
JPS6278853A (en) * 1985-09-30 1987-04-11 Nec Corp Manufacture of semiconductor device
JPH0620101B2 (en) * 1986-09-29 1994-03-16 三菱電機株式会社 Semiconductor device
GB2206729B (en) * 1987-07-01 1990-10-24 British Aerospace A method of forming electrical contacts in a multi-level interconnect system
JP2666932B2 (en) * 1987-09-28 1997-10-22 株式会社東芝 Method for manufacturing semiconductor device
JPH01289142A (en) * 1988-05-16 1989-11-21 Nippon Telegr & Teleph Corp <Ntt> Vertical wiring structure
GB2219434A (en) * 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device

Also Published As

Publication number Publication date
GB9013153D0 (en) 1990-08-01
JPH03203323A (en) 1991-09-05
DE4018437A1 (en) 1991-07-11
GB2239559A (en) 1991-07-03

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SUBM Submission of document of abandonment before or after decision of registration