DE60031631D1 - Verfahren zum Vermeiden von Kupfer-Kontamination der Seitenflächen eines Kontaktloches oder einer Doppel-Damaszenen-Struktur - Google Patents
Verfahren zum Vermeiden von Kupfer-Kontamination der Seitenflächen eines Kontaktloches oder einer Doppel-Damaszenen-StrukturInfo
- Publication number
- DE60031631D1 DE60031631D1 DE60031631T DE60031631T DE60031631D1 DE 60031631 D1 DE60031631 D1 DE 60031631D1 DE 60031631 T DE60031631 T DE 60031631T DE 60031631 T DE60031631 T DE 60031631T DE 60031631 D1 DE60031631 D1 DE 60031631D1
- Authority
- DE
- Germany
- Prior art keywords
- dielectric layer
- overlying
- layer
- copper metallization
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title abstract 10
- 229910052802 copper Inorganic materials 0.000 title abstract 10
- 239000010949 copper Substances 0.000 title abstract 10
- 238000011109 contamination Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 title abstract 3
- 238000001465 metallisation Methods 0.000 abstract 7
- 230000009977 dual effect Effects 0.000 abstract 3
- 238000005530 etching Methods 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 2
- 229910052751 metal Inorganic materials 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US439361 | 1995-05-11 | ||
US09/439,361 US6114243A (en) | 1999-11-15 | 1999-11-15 | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60031631D1 true DE60031631D1 (de) | 2006-12-14 |
DE60031631T2 DE60031631T2 (de) | 2007-08-16 |
Family
ID=23744411
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60031631T Expired - Lifetime DE60031631T2 (de) | 1999-11-15 | 2000-11-13 | Verfahren zum Vermeiden von Kupfer-Kontamination der Seitenflächen eines Kontaktloches oder einer Doppel-Damaszenen-Struktur |
Country Status (6)
Country | Link |
---|---|
US (1) | US6114243A (de) |
EP (1) | EP1102315B1 (de) |
JP (1) | JP2001156073A (de) |
AT (1) | ATE344534T1 (de) |
DE (1) | DE60031631T2 (de) |
SG (1) | SG126670A1 (de) |
Families Citing this family (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3545177B2 (ja) * | 1997-09-18 | 2004-07-21 | 株式会社荏原製作所 | 多層埋め込みCu配線形成方法 |
JP3164214B2 (ja) * | 1998-11-04 | 2001-05-08 | 日本電気株式会社 | 金属膜の研磨方法 |
JP3708732B2 (ja) | 1998-12-25 | 2005-10-19 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6383917B1 (en) * | 1999-10-21 | 2002-05-07 | Intel Corporation | Method for making integrated circuits |
TW490718B (en) * | 2000-01-25 | 2002-06-11 | Toshiba Corp | Semiconductor device and the manufacturing method thereof |
JP4342075B2 (ja) * | 2000-03-28 | 2009-10-14 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6537912B1 (en) | 2000-08-25 | 2003-03-25 | Micron Technology Inc. | Method of forming an encapsulated conductive pillar |
US6294463B1 (en) * | 2000-09-13 | 2001-09-25 | Vanguard International Semiconductor Corp. | Method for manufacturing diffusion barrier layer |
US6406996B1 (en) * | 2000-09-30 | 2002-06-18 | Advanced Micro Devices, Inc. | Sub-cap and method of manufacture therefor in integrated circuit capping layers |
AU2001279032A1 (en) * | 2000-11-14 | 2002-05-27 | Advanced Micro Devices Inc. | Method of forming conductive interconnections wherein a barrier layer is removed by an etching process |
US6436814B1 (en) * | 2000-11-21 | 2002-08-20 | International Business Machines Corporation | Interconnection structure and method for fabricating same |
US6709874B2 (en) * | 2001-01-24 | 2004-03-23 | Infineon Technologies Ag | Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation |
US6632707B1 (en) * | 2001-01-31 | 2003-10-14 | Advanced Micro Devices, Inc. | Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning |
KR100385227B1 (ko) * | 2001-02-12 | 2003-05-27 | 삼성전자주식회사 | 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법 |
US6649517B2 (en) | 2001-05-18 | 2003-11-18 | Chartered Semiconductor Manufacturing Ltd. | Copper metal structure for the reduction of intra-metal capacitance |
US6489240B1 (en) * | 2001-05-31 | 2002-12-03 | Advanced Micro Devices, Inc. | Method for forming copper interconnects |
JP2002367998A (ja) * | 2001-06-11 | 2002-12-20 | Ebara Corp | 半導体装置及びその製造方法 |
US6537913B2 (en) * | 2001-06-29 | 2003-03-25 | Intel Corporation | Method of making a semiconductor device with aluminum capped copper interconnect pads |
US6461914B1 (en) * | 2001-08-29 | 2002-10-08 | Motorola, Inc. | Process for making a MIM capacitor |
US6617152B2 (en) * | 2001-09-04 | 2003-09-09 | Corning Inc | Method for creating a cell growth surface on a polymeric substrate |
JP4198906B2 (ja) * | 2001-11-15 | 2008-12-17 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の製造方法 |
US20060234508A1 (en) * | 2002-05-17 | 2006-10-19 | Mitsuhiko Shirakashi | Substrate processing apparatus and substrate processing method |
KR100474857B1 (ko) * | 2002-06-29 | 2005-03-10 | 매그나칩 반도체 유한회사 | 반도체 소자의 구리 배선 형성방법 |
KR100475931B1 (ko) * | 2002-07-02 | 2005-03-10 | 매그나칩 반도체 유한회사 | 반도체 소자의 다층 배선 형성방법 |
US20040048468A1 (en) * | 2002-09-10 | 2004-03-11 | Chartered Semiconductor Manufacturing Ltd. | Barrier metal cap structure on copper lines and vias |
US7005375B2 (en) * | 2002-09-30 | 2006-02-28 | Agere Systems Inc. | Method to avoid copper contamination of a via or dual damascene structure |
US7144811B2 (en) * | 2002-10-03 | 2006-12-05 | Taiwan Semiconductor Manufacturing Co. Ltd | Method of forming a protective layer over Cu filled semiconductor features |
US6919639B2 (en) * | 2002-10-15 | 2005-07-19 | The Board Of Regents, The University Of Texas System | Multiple copper vias for integrated circuit metallization and methods of fabricating same |
US6884728B2 (en) * | 2002-11-06 | 2005-04-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for removing polymeric residue contamination on semiconductor feature sidewalls |
US6706625B1 (en) | 2002-12-06 | 2004-03-16 | Chartered Semiconductor Manufacturing Ltd. | Copper recess formation using chemical process for fabricating barrier cap for lines and vias |
US20040121583A1 (en) * | 2002-12-19 | 2004-06-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming capping barrier layer over copper feature |
KR100641502B1 (ko) * | 2002-12-30 | 2006-10-31 | 동부일렉트로닉스 주식회사 | 반도체 소자 제조시 듀얼 다마신 공정을 이용한 콘텍형성방법 |
US20040219298A1 (en) * | 2003-02-27 | 2004-11-04 | Akira Fukunaga | Substrate processing method and substrate processing apparatus |
AU2003220989A1 (en) * | 2003-03-28 | 2004-10-25 | Fujitsu Limited | Semiconductor device |
US20040248405A1 (en) * | 2003-06-02 | 2004-12-09 | Akira Fukunaga | Method of and apparatus for manufacturing semiconductor device |
JP2005038971A (ja) * | 2003-07-17 | 2005-02-10 | Ebara Corp | 半導体装置及びその製造方法 |
JP4041785B2 (ja) * | 2003-09-26 | 2008-01-30 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US20050130407A1 (en) * | 2003-12-12 | 2005-06-16 | Jui-Neng Tu | Dual damascene process for forming a multi-layer low-k dielectric interconnect |
US20050173799A1 (en) * | 2004-02-05 | 2005-08-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method for its fabricating |
US7300875B2 (en) * | 2004-02-11 | 2007-11-27 | Infineon Technologies Richmond, Lp | Post metal chemical mechanical polishing dry cleaning |
US7071564B1 (en) * | 2004-03-04 | 2006-07-04 | Advanced Micro Devices, Inc. | Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration |
US20050194683A1 (en) * | 2004-03-08 | 2005-09-08 | Chen-Hua Yu | Bonding structure and fabrication thereof |
JP4235841B2 (ja) * | 2004-05-14 | 2009-03-11 | 日本電気株式会社 | 信号処理装置および信号処理方法 |
JP4503401B2 (ja) * | 2004-09-08 | 2010-07-14 | 株式会社荏原製作所 | 金属膜の成膜方法及び配線の形成方法 |
US7176119B2 (en) * | 2004-09-20 | 2007-02-13 | International Business Machines Corporation | Method of fabricating copper damascene and dual damascene interconnect wiring |
US7833896B2 (en) * | 2004-09-23 | 2010-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Aluminum cap for reducing scratch and wire-bond bridging of bond pads |
WO2006059261A2 (en) | 2004-12-01 | 2006-06-08 | Koninklijke Philips Electronics N.V. | A method of forming an interconnect structure on an integrated circuit die |
KR100668833B1 (ko) * | 2004-12-17 | 2007-01-16 | 주식회사 하이닉스반도체 | 반도체소자의 캐패시터 제조방법 |
JP4618786B2 (ja) * | 2005-01-28 | 2011-01-26 | キヤノン株式会社 | 固体撮像装置の製造方法 |
US20060205204A1 (en) * | 2005-03-14 | 2006-09-14 | Michael Beck | Method of making a semiconductor interconnect with a metal cap |
JP2006324414A (ja) * | 2005-05-18 | 2006-11-30 | Toshiba Corp | 半導体装置及びその製造方法 |
US20070049009A1 (en) * | 2005-08-30 | 2007-03-01 | Chia-Lin Hsu | Method of manufacturing conductive layer |
DE102005046975A1 (de) * | 2005-09-30 | 2007-04-05 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Herstellung einer kupferbasierten Metallisierungsschicht mit einer leitenden Deckschicht |
KR100729126B1 (ko) * | 2005-11-15 | 2007-06-14 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 및 그 형성 방법 |
US7960838B2 (en) * | 2005-11-18 | 2011-06-14 | United Microelectronics Corp. | Interconnect structure |
TWI312152B (en) * | 2006-01-04 | 2009-07-11 | Ind Tech Res Inst | Method for manufacturing a semiconductor device |
DE102006025405B4 (de) * | 2006-05-31 | 2018-03-29 | Globalfoundries Inc. | Verfahren zur Herstellung einer Metallisierungsschicht eines Halbleiterbauelements mit unterschiedlich dicken Metallleitungen |
DE102007004860B4 (de) * | 2007-01-31 | 2008-11-06 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Kupfer-basierten Metallisierungsschicht mit einer leitenden Deckschicht durch ein verbessertes Integrationsschema |
US7880303B2 (en) * | 2007-02-13 | 2011-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked contact with low aspect ratio |
DE102007009912B4 (de) * | 2007-02-28 | 2009-06-10 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer kupferbasierten Metallisierungsschicht mit einer leitenden Deckschicht durch ein fortschrittliches Integrationsschema |
CN101295644A (zh) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | 铜表面化学机械研磨平坦化方法 |
US8264072B2 (en) * | 2007-10-22 | 2012-09-11 | Infineon Technologies Ag | Electronic device |
US8575000B2 (en) * | 2011-07-19 | 2013-11-05 | SanDisk Technologies, Inc. | Copper interconnects separated by air gaps and method of making thereof |
US8772949B2 (en) | 2012-11-07 | 2014-07-08 | International Business Machines Corporation | Enhanced capture pads for through semiconductor vias |
WO2017111820A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Reduced height liner for interconnects |
US10109524B2 (en) * | 2017-01-24 | 2018-10-23 | Globalfoundries Inc. | Recessing of liner and conductor for via formation |
US10347529B2 (en) * | 2017-10-04 | 2019-07-09 | Globalfoundries Inc. | Interconnect structures |
US11164779B2 (en) * | 2019-04-12 | 2021-11-02 | International Business Machines Corporation | Bamboo tall via interconnect structures |
KR102678758B1 (ko) | 2019-11-06 | 2024-06-27 | 삼성전자주식회사 | 반도체 소자 |
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DE69220559T2 (de) * | 1991-12-18 | 1997-12-18 | Sgs Thomson Microelectronics | Verfahren zur Herstellung von Kontakten in Löchern in integrierten Schaltungen |
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5262354A (en) * | 1992-02-26 | 1993-11-16 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5371047A (en) * | 1992-10-30 | 1994-12-06 | International Business Machines Corporation | Chip interconnection having a breathable etch stop layer |
JP3326698B2 (ja) * | 1993-03-19 | 2002-09-24 | 富士通株式会社 | 集積回路装置の製造方法 |
US5380546A (en) * | 1993-06-09 | 1995-01-10 | Microelectronics And Computer Technology Corporation | Multilevel metallization process for electronic components |
DE69529775T2 (de) * | 1994-08-05 | 2003-10-16 | International Business Machines Corp., Armonk | Verfahren zur Herstellung einer Damaszenstruktur mit einer WGe Polierstoppschicht |
JP2728025B2 (ja) * | 1995-04-13 | 1998-03-18 | 日本電気株式会社 | 半導体装置の製造方法 |
US5744376A (en) * | 1996-04-08 | 1998-04-28 | Chartered Semiconductor Manufacturing Pte, Ltd | Method of manufacturing copper interconnect with top barrier layer |
US5891804A (en) * | 1996-04-18 | 1999-04-06 | Texas Instruments Incorporated | Process for conductors with selective deposition |
US5814557A (en) * | 1996-05-20 | 1998-09-29 | Motorola, Inc. | Method of forming an interconnect structure |
JP3607424B2 (ja) * | 1996-07-12 | 2005-01-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5693563A (en) * | 1996-07-15 | 1997-12-02 | Chartered Semiconductor Manufacturing Pte Ltd. | Etch stop for copper damascene process |
US5942449A (en) * | 1996-08-28 | 1999-08-24 | Micron Technology, Inc. | Method for removing an upper layer of material from a semiconductor wafer |
JPH10242271A (ja) * | 1997-02-28 | 1998-09-11 | Sony Corp | 半導体装置及びその製造方法 |
JP3228181B2 (ja) * | 1997-05-12 | 2001-11-12 | ヤマハ株式会社 | 平坦配線形成法 |
US6069068A (en) * | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
US5976967A (en) * | 1998-02-13 | 1999-11-02 | Texas Instruments - Acer Incorporated | Dual damascene process for multi-level metallization and interconnection structure |
US5939788A (en) * | 1998-03-11 | 1999-08-17 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper |
TW396524B (en) * | 1998-06-26 | 2000-07-01 | United Microelectronics Corp | A method for fabricating dual damascene |
US6004188A (en) * | 1998-09-10 | 1999-12-21 | Chartered Semiconductor Manufacturing Ltd. | Method for forming copper damascene structures by using a dual CMP barrier layer |
-
1999
- 1999-11-15 US US09/439,361 patent/US6114243A/en not_active Expired - Lifetime
-
2000
- 2000-06-16 SG SG200003416A patent/SG126670A1/en unknown
- 2000-08-02 JP JP2000234284A patent/JP2001156073A/ja active Pending
- 2000-11-13 EP EP00640011A patent/EP1102315B1/de not_active Expired - Lifetime
- 2000-11-13 DE DE60031631T patent/DE60031631T2/de not_active Expired - Lifetime
- 2000-11-13 AT AT00640011T patent/ATE344534T1/de not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE60031631T2 (de) | 2007-08-16 |
JP2001156073A (ja) | 2001-06-08 |
SG126670A1 (en) | 2006-11-29 |
EP1102315A2 (de) | 2001-05-23 |
EP1102315B1 (de) | 2006-11-02 |
EP1102315A3 (de) | 2003-09-24 |
ATE344534T1 (de) | 2006-11-15 |
US6114243A (en) | 2000-09-05 |
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