AU2001279032A1 - Method of forming conductive interconnections wherein a barrier layer is removed by an etching process - Google Patents

Method of forming conductive interconnections wherein a barrier layer is removed by an etching process

Info

Publication number
AU2001279032A1
AU2001279032A1 AU2001279032A AU7903201A AU2001279032A1 AU 2001279032 A1 AU2001279032 A1 AU 2001279032A1 AU 2001279032 A AU2001279032 A AU 2001279032A AU 7903201 A AU7903201 A AU 7903201A AU 2001279032 A1 AU2001279032 A1 AU 2001279032A1
Authority
AU
Australia
Prior art keywords
barrier layer
etching process
forming conductive
conductive interconnections
interconnections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001279032A
Inventor
Peter J. Beckage
Paul R. Besser
William S. Brennan
Frederick N. Hause
John A. Iacoponi
Frank Mauersberger
Errol Todd Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001279032A1 publication Critical patent/AU2001279032A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AU2001279032A 2000-11-14 2001-07-26 Method of forming conductive interconnections wherein a barrier layer is removed by an etching process Abandoned AU2001279032A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US71264300A 2000-11-14 2000-11-14
US09/712,643 2000-11-14
PCT/US2001/023578 WO2002041368A2 (en) 2000-11-14 2001-07-26 Method of forming conductive interconnections wherein a barrier layer is removed by an etching process

Publications (1)

Publication Number Publication Date
AU2001279032A1 true AU2001279032A1 (en) 2002-05-27

Family

ID=24862964

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001279032A Abandoned AU2001279032A1 (en) 2000-11-14 2001-07-26 Method of forming conductive interconnections wherein a barrier layer is removed by an etching process

Country Status (2)

Country Link
AU (1) AU2001279032A1 (en)
WO (1) WO2002041368A2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW367585B (en) * 1997-12-19 1999-08-21 Promos Technologies Inc Method for completely removing the titanium nitride residuals outside the integrated circuit contacts
US6140234A (en) * 1998-01-20 2000-10-31 International Business Machines Corporation Method to selectively fill recesses with conductive metal
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure

Also Published As

Publication number Publication date
WO2002041368A2 (en) 2002-05-23
WO2002041368A3 (en) 2002-08-29

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