AU2002235754A1 - A method for producing soi wafers by delamination - Google Patents

A method for producing soi wafers by delamination

Info

Publication number
AU2002235754A1
AU2002235754A1 AU2002235754A AU3575402A AU2002235754A1 AU 2002235754 A1 AU2002235754 A1 AU 2002235754A1 AU 2002235754 A AU2002235754 A AU 2002235754A AU 3575402 A AU3575402 A AU 3575402A AU 2002235754 A1 AU2002235754 A1 AU 2002235754A1
Authority
AU
Australia
Prior art keywords
delamination
soi wafers
producing soi
producing
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002235754A
Inventor
Peter Stanley
Timothy Stanley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2002235754A1 publication Critical patent/AU2002235754A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
AU2002235754A 2000-12-04 2001-12-03 A method for producing soi wafers by delamination Abandoned AU2002235754A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/729,502 2000-12-04
US09/729,502 US6420243B1 (en) 2000-12-04 2000-12-04 Method for producing SOI wafers by delamination
PCT/EP2001/014258 WO2002047136A2 (en) 2000-12-04 2001-12-03 A method for producing soi wafers by delamination

Publications (1)

Publication Number Publication Date
AU2002235754A1 true AU2002235754A1 (en) 2002-06-18

Family

ID=24931335

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002235754A Abandoned AU2002235754A1 (en) 2000-12-04 2001-12-03 A method for producing soi wafers by delamination

Country Status (3)

Country Link
US (1) US6420243B1 (en)
AU (1) AU2002235754A1 (en)
WO (1) WO2002047136A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PT733109E (en) * 1993-12-07 2006-07-31 Genetics Inst Llc MORPHOGENETIC PROTEINS OF 0SS0S PMO-12 AND PMO-13 AND THEIR COMPOSITIONS FOR TENDAO INDUCTION
JP4304879B2 (en) * 2001-04-06 2009-07-29 信越半導体株式会社 Method for determining the implantation amount of hydrogen ions or rare gas ions
FR2855909B1 (en) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator PROCESS FOR THE CONCURRENT PRODUCTION OF AT LEAST ONE PAIR OF STRUCTURES COMPRISING AT LEAST ONE USEFUL LAYER REPORTED ON A SUBSTRATE
FR2855910B1 (en) * 2003-06-06 2005-07-15 Commissariat Energie Atomique PROCESS FOR OBTAINING A VERY THIN LAYER BY SELF-CURING BY PROVOQUE SELF-CURING
DE102006007293B4 (en) 2006-01-31 2023-04-06 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Method for producing a quasi-substrate wafer and a semiconductor body produced using such a quasi-substrate wafer
EP2157602A1 (en) * 2008-08-20 2010-02-24 Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. A method of manufacturing a plurality of fabrication wafers
US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2738671B1 (en) 1995-09-13 1997-10-10 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS WITH SEMICONDUCTOR MATERIAL
CN1132223C (en) * 1995-10-06 2003-12-24 佳能株式会社 Semiconductor substrate and producing method thereof
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
CA2220600C (en) * 1996-11-15 2002-02-12 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
CA2233096C (en) * 1997-03-26 2003-01-07 Canon Kabushiki Kaisha Substrate and production method thereof
US5949108A (en) * 1997-06-30 1999-09-07 Intel Corporation Semiconductor device with reduced capacitance
US5882987A (en) 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US5920764A (en) * 1997-09-30 1999-07-06 International Business Machines Corporation Process for restoring rejected wafers in line for reuse as new
JP3697106B2 (en) * 1998-05-15 2005-09-21 キヤノン株式会社 Method for manufacturing semiconductor substrate and method for manufacturing semiconductor thin film
JP3358550B2 (en) * 1998-07-07 2002-12-24 信越半導体株式会社 Method for producing SOI wafer and SOI wafer produced by this method
JP3395661B2 (en) * 1998-07-07 2003-04-14 信越半導体株式会社 Method for manufacturing SOI wafer
JP3385972B2 (en) * 1998-07-10 2003-03-10 信越半導体株式会社 Manufacturing method of bonded wafer and bonded wafer
WO2000063965A1 (en) * 1999-04-21 2000-10-26 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
JP4450126B2 (en) * 2000-01-21 2010-04-14 日新電機株式会社 Method for forming silicon crystal thin film

Also Published As

Publication number Publication date
US6420243B1 (en) 2002-07-16
WO2002047136A2 (en) 2002-06-13
WO2002047136A3 (en) 2003-06-19
US20020068418A1 (en) 2002-06-06

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