AU2003299875A1 - Method of forming a catalyst containing layer over a patterned dielectric - Google Patents
Method of forming a catalyst containing layer over a patterned dielectricInfo
- Publication number
- AU2003299875A1 AU2003299875A1 AU2003299875A AU2003299875A AU2003299875A1 AU 2003299875 A1 AU2003299875 A1 AU 2003299875A1 AU 2003299875 A AU2003299875 A AU 2003299875A AU 2003299875 A AU2003299875 A AU 2003299875A AU 2003299875 A1 AU2003299875 A1 AU 2003299875A1
- Authority
- AU
- Australia
- Prior art keywords
- forming
- containing layer
- layer over
- catalyst containing
- patterned dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000003054 catalyst Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10302644A DE10302644B3 (en) | 2003-01-23 | 2003-01-23 | Process for producing a metal layer over a structured dielectric by means of electroless deposition using a catalyst |
DE10302644.4 | 2003-01-23 | ||
US10/602,192 | 2003-06-24 | ||
US10/602,192 US6951816B2 (en) | 2003-01-23 | 2003-06-24 | Method of forming a metal layer over patterned dielectric by electroless deposition using a catalyst |
PCT/US2003/041185 WO2004068576A2 (en) | 2003-01-23 | 2003-12-22 | Method of forming a catalyst containing layer over a patterned dielectric |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2003299875A1 true AU2003299875A1 (en) | 2004-08-23 |
Family
ID=32826166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2003299875A Abandoned AU2003299875A1 (en) | 2003-01-23 | 2003-12-22 | Method of forming a catalyst containing layer over a patterned dielectric |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP5214092B2 (en) |
KR (1) | KR101098568B1 (en) |
AU (1) | AU2003299875A1 (en) |
GB (1) | GB2417132B (en) |
WO (1) | WO2004068576A2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6943106B1 (en) * | 2004-02-20 | 2005-09-13 | Micron Technology, Inc. | Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling |
JP2006128288A (en) * | 2004-10-27 | 2006-05-18 | Tokyo Electron Ltd | Film forming method, semiconductor device, manufacturing method thereof, program, and recording medium |
JP4376958B2 (en) | 2007-07-31 | 2009-12-02 | 日鉱金属株式会社 | Plating object in which metal thin film is formed by electroless plating and manufacturing method thereof |
WO2010087392A1 (en) * | 2009-01-30 | 2010-08-05 | 日鉱金属株式会社 | Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power |
US20220344205A1 (en) * | 2019-09-25 | 2022-10-27 | Tokyo Electron Limited | Substrate liquid processing method and substate liquid processing apparatus |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4574095A (en) * | 1984-11-19 | 1986-03-04 | International Business Machines Corporation | Selective deposition of copper |
JPH0762545A (en) * | 1993-08-30 | 1995-03-07 | Mitsubishi Cable Ind Ltd | Wiring board and its production |
US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
US6197688B1 (en) * | 1998-02-12 | 2001-03-06 | Motorola Inc. | Interconnect structure in a semiconductor device and method of formation |
US6461675B2 (en) * | 1998-07-10 | 2002-10-08 | Cvc Products, Inc. | Method for forming a copper film on a substrate |
US6380083B1 (en) * | 1998-08-28 | 2002-04-30 | Agere Systems Guardian Corp. | Process for semiconductor device fabrication having copper interconnects |
US6610596B1 (en) * | 1999-09-15 | 2003-08-26 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
JP2001240960A (en) * | 1999-12-21 | 2001-09-04 | Nippon Sheet Glass Co Ltd | Article coated with photocatalytic film, method of manufacturing for the article, and sputtering target used for depositing the film |
KR100338112B1 (en) * | 1999-12-22 | 2002-05-24 | 박종섭 | Method of forming a copper wiring in a semiconductor device |
WO2001049898A1 (en) * | 2000-01-07 | 2001-07-12 | Nikko Materials Co., Ltd. | Method for metal plating, pre-treating agent, and semiconductor wafer and semiconductor device using the same |
JP2001335952A (en) * | 2000-05-31 | 2001-12-07 | Rikogaku Shinkokai | Electroless plating method, wiring device and its production method |
JP2002004081A (en) * | 2000-06-16 | 2002-01-09 | Learonal Japan Inc | Electroplating method to silicon wafer |
US6479902B1 (en) * | 2000-06-29 | 2002-11-12 | Advanced Micro Devices, Inc. | Semiconductor catalytic layer and atomic layer deposition thereof |
JP2002025943A (en) * | 2000-07-12 | 2002-01-25 | Ebara Corp | Substrate film forming method |
JP2002053971A (en) * | 2000-08-03 | 2002-02-19 | Sony Corp | Plating method, plating structure, method for producing semiconductor device, and semiconductor device |
EP1180553A1 (en) * | 2000-08-15 | 2002-02-20 | Air Products And Chemicals, Inc. | CVD process for depositing copper on a barrier layer |
JP4083968B2 (en) * | 2000-11-02 | 2008-04-30 | 株式会社東芝 | Manufacturing method of semiconductor device |
US20020064592A1 (en) * | 2000-11-29 | 2002-05-30 | Madhav Datta | Electroless method of seed layer depostion, repair, and fabrication of Cu interconnects |
US6596344B2 (en) * | 2001-03-27 | 2003-07-22 | Sharp Laboratories Of America, Inc. | Method of depositing a high-adhesive copper thin film on a metal nitride substrate |
-
2003
- 2003-12-22 KR KR1020057013668A patent/KR101098568B1/en active IP Right Grant
- 2003-12-22 JP JP2004567443A patent/JP5214092B2/en not_active Expired - Lifetime
- 2003-12-22 GB GB0513698A patent/GB2417132B/en not_active Expired - Lifetime
- 2003-12-22 WO PCT/US2003/041185 patent/WO2004068576A2/en active Application Filing
- 2003-12-22 AU AU2003299875A patent/AU2003299875A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
GB2417132B (en) | 2007-04-04 |
JP5214092B2 (en) | 2013-06-19 |
JP2006513325A (en) | 2006-04-20 |
GB0513698D0 (en) | 2005-08-10 |
KR101098568B1 (en) | 2011-12-26 |
GB2417132A (en) | 2006-02-15 |
KR20050088363A (en) | 2005-09-05 |
WO2004068576A3 (en) | 2004-09-10 |
WO2004068576A2 (en) | 2004-08-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |