GB2401483B - A method of etching porous dielectric - Google Patents
A method of etching porous dielectricInfo
- Publication number
- GB2401483B GB2401483B GB0408408A GB0408408A GB2401483B GB 2401483 B GB2401483 B GB 2401483B GB 0408408 A GB0408408 A GB 0408408A GB 0408408 A GB0408408 A GB 0408408A GB 2401483 B GB2401483 B GB 2401483B
- Authority
- GB
- United Kingdom
- Prior art keywords
- porous dielectric
- etching porous
- etching
- dielectric
- porous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005530 etching Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0310238 | 2003-05-03 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0408408D0 GB0408408D0 (en) | 2004-05-19 |
GB2401483A GB2401483A (en) | 2004-11-10 |
GB2401483B true GB2401483B (en) | 2006-04-19 |
Family
ID=32320344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0408408A Expired - Fee Related GB2401483B (en) | 2003-05-03 | 2004-04-15 | A method of etching porous dielectric |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2004336038A (en) |
DE (1) | DE102004017533A1 (en) |
GB (1) | GB2401483B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8435901B2 (en) * | 2010-06-11 | 2013-05-07 | Tokyo Electron Limited | Method of selectively etching an insulation stack for a metal interconnect |
CN102832118B (en) * | 2012-09-11 | 2015-02-18 | 上海华力微电子有限公司 | Method for etching bottom anti-reflective coating in dual damascene structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002049089A1 (en) * | 2000-12-14 | 2002-06-20 | Tokyo Electron Limited | Method of etching porous insulating film, dual damascene process, and semiconductor device |
-
2004
- 2004-04-08 DE DE102004017533A patent/DE102004017533A1/en not_active Withdrawn
- 2004-04-15 GB GB0408408A patent/GB2401483B/en not_active Expired - Fee Related
- 2004-04-28 JP JP2004133210A patent/JP2004336038A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002049089A1 (en) * | 2000-12-14 | 2002-06-20 | Tokyo Electron Limited | Method of etching porous insulating film, dual damascene process, and semiconductor device |
Non-Patent Citations (1)
Title |
---|
H Donohue et al, Preparation of damascene trench sidewalls in CVD nano-porous ultra low K(=2.2) films for compatibility with MOCVD diffusion barriers, http://www.trikon.com/pdfs/Donohue_AMC_2002_paper.pdf * |
Also Published As
Publication number | Publication date |
---|---|
JP2004336038A (en) | 2004-11-25 |
DE102004017533A1 (en) | 2005-01-13 |
GB0408408D0 (en) | 2004-05-19 |
GB2401483A (en) | 2004-11-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20110415 |