WO2002041368A2

WO2002041368A2 - Method of forming conductive interconnections wherein a barrier layer is removed by an etching process

Info

Publication number: WO2002041368A2
Application number: PCT/US2001/023578
Authority: WO
Inventors: Errol Todd Ryan; Paul R. Besser; Frederick N. Hause; Frank Mauersberger; William S. Brennan; John A. Iacoponi; Peter J. Beckage
Original assignee: Advanced Micro Devices, Inc.
Priority date: 2000-11-14
Filing date: 2001-07-26
Publication date: 2002-05-23
Also published as: AU2001279032A1; WO2002041368A3

Abstract

The present invention is directed to a method of removing barrier layers by performing an etching process instead of a CMP process. In one embodiment, the method comprises forming a layer of insulating material 20, forming an opening 22 in the layer of insulating material 20, and forming a barrier layer 26 above an upper surface 25 of the insulating layer 20 and in the opening 22. The method further comprises forming a conductive material above the upper surface 27 of the barrier layer 26 and in the opening 22, performing a CMP process to remove substantially all of the conductive material positioned above the upper surface 27 of the barrier layer 26, performing at least one etching process on the barrier layer 26 to remove substantially all of the barrier layer 26 positioned above the upper surface 25 of the insulating layer 20, and, in some cases, performing at least one chemical mechanical polishing operation to remove at least a portion of the conductive material positioned outside of the opening 22 and above the upper surface 25 of the insulating layer 20 to define a conductive interconnection positioned within the opening 22 in the insulating layer 20.

Description

METHOD OF FORMING CONDUCTIVE INTERCONNECTIONS WHEREIN A BARRIER LAYER IS

REMOVED BY AN ETCHING PROCESS

TECHNICAL FIELD

The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to a method of forming conductive interconnections without performing chemical mechanical polishing operations to remove portions of a barrier layer that is formed as part of the process of forming the conductive interconnections.

BACKGROUND ART

There is a constant drive to reduce the size, or scale, of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of millions of transistors formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections, i.e., conductive lines and plugs.

Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of alternating layers of conductive lines and conductive plugs formed in layers of insulating materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.

A typical prior art process flow for forming such conductive interconnections will now be described. As shown in Figure 1A, a layer of insulating material 10, e.g., silicon dioxide, may be formed above a transistor (not shown) that was previously formed above a semiconducting substrate (not shown), or it may be formed above a previously formed layer of insulating material (not shown) having conductive interconnections formed therein. Next, an opening 12, defined by sidewalls 14, is formed in the layer of insulating material 10. Thereafter, a barrier layer 16 is formed above a surface 17 of the insulating layer 10 and in the opening 12. The insulating material 10 may be any type of material sufficient for serving insulative functions, e.g., an oxide, an oxynitride, silicon dioxide, silicon oxynitride, a fluorinated oxide, etc. The barrier layer 16 may be comprised of a material sufficient to serve its intended function of preventing migration of the material that will comprise the conductive line or plug into unwanted areas of the device. In one illustrative embodiment, the barrier layer 16 is comprised of tantalum. Such a tantalum barrier layer may be used where conductive interconnections comprised of copper will be formed. In some situations, the barrier layer 16 may be comprised of two or more layers of material, e.g, a titanium/titanium nitride bi-layer, although that is not depicted in Figure 1A.

Next, as shown in Figure IB, a layer of conductive material 18 is formed above the barrier layer 16 and in the opening 12. The conductive material 18 may be comprised of a variety of materials, e.g., copper, tantalum, tungsten, aluminum, etc. In the case where the conductive material 18 is comprised of copper, prior to its formation, a copper seed layer (not shown) may be formed above the barrier layer 16 depicted in Figure 1A. Thereafter, using known electroplating techniques, the conductive layer 18 comprised of copper may be formed above the structure depicted in Figure 1A. In situations where the conductive layer 18 is comprised of another material, e.g., tungsten, the layer of conductive material 18 may be directly deposited on the barrier layer 16 and into the opening 12.

Thereafter, one or more chemical mechanical polishing ("CMP") operations are performed to remove portions of the conductive layer 18 and the barrier layer 16 lying outside of the opening 12 above the surface 17 of the insulating layer 10 to define a conductive interconnection 19. That is, CMP operations may be performed until a surface 13 of the conductive interconnection 19 is approximately planar with the surface 17 of the insulating layer 10. During these CMP operations, portions of the barrier layer 16 positioned above the surface 17 of the insulating layer 10 are also removed. Typically, in the case of conductive interconnections comprised of copper, one or two CMP processes will be performed to remove substantially all of the copper, and an additional CMP operation will be performed to remove portions of the barrier layer 16 lying above the surface 17 of the insulating layer 10.

As stated previously, there is a constant drive to increase the operating speed of integrated circuit devices. One result of this drive is that the insulating layer 10 is often comprised of materials having a relatively low dielectric constant so that capacitive coupling between adjacent conductive lines may be reduced. However, many of these so-called "low-k" materials are mechanically weak and tend to suffer adhesion and cohesion failures during CMP processing operations, particularly during the barrier layer CMP operation. This is a result of the large shear forces induced during these CMP operations. The deterioration and/or destruction of portions of the insulating layer 10 during these processes may be problematic in that insufficient insulation is provided around the completed conductive interconnections. Moreover, the destruction or depletion of a portion of the insulating layer 10 may result in the formation of conductive materials in areas where insulating materials are expected to be formed. These types of problems may lead to reduced device performance and/or failure.

The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.

DISCLOSURE OF INVENTION

The present invention is directed to a method of removing portions of barrier layers commonly used in the process of forming conductive interconnections on an integrated circuit device by means of an etching process instead of a CMP process. In one illustrative embodiment, the method comprises forming a layer of insulating material, forming an opening in the layer of insulating material, and forming a barrier layer above an upper surface of the insulating layer and in the opening. The method further comprises forming a conductive material above the upper surface of the barrier layer and in the opening, performing a CMP process to remove substantially all of the conductive material positioned above an upper surface of the barrier layer, and performing at least one etching process on the barrier layer to remove substantially all of the barrier layer positioned above the upper surface of the insulating layer. If deemed necessary, the method may further comprise performing at least one chemical mechanical polishing operation to remove at least a portion of the conductive material positioned outside of the opening and above the upper surface of the insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

Figures 1A-1C depict an illustrative process flow for forming conductive interconnections where the barrier layer used in forming the interconnection is removed by a chemical mechanical polishing operation; and

Figures 2A-2E depict one illustrative embodiment of the inventive method disclosed herein. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

MODE(S) FOR CARRYING OUT THE INVENTION

Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present invention will now be described with reference to Figures 2A-2E. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features and regions depicted in the drawings may be exaggerated or reduced as compared to the size of those features or regions on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention.

In general, the present invention is directed to a method of forming conductive interconnections where portions of the barrier layer are removed by an etchback process instead of a CMP process. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. Moreover, the present invention may be used with a variety of combinations of materials for the insulating layer, the barrier layer and the conductive materials used to form the conductive interconnections.

, As shown in Figure 2A, an opening 22, having sidewalls 24, is formed in an insulating layer 20 having a top surface 25. The insulating layer 20 may be positioned above a transistor (not shown) that was previously formed above a surface of a semiconducting substrate (not shown), or it may be formed above a previously formed layer of insulating material (not shown) having conductive interconnections formed therein. The insulating layer 20 may be comprised of a variety of insulating materials, e.g., an oxide, an oxynitride, silicon dioxide, silicon oxynitride, a fluorinated oxide, Applied Materials' Black Diamond^® product, Dow Chemical's SiLK^® product, insulating materials having a dielectric constant less than approximately 4, or any other material sufficient for serving its insulative purpose. The insulating layer 20 may be formed by a variety of techniques, such as chemical vapor deposition ("CVD"), low pressure chemical vapor deposition ("LPCVD"), spin-coating, sputtering, thermal growing, etc. Moreover, the insulating layer 20 may have a variety of thicknesses. Thus, the particular materials of construction of the insulating layer 20, and the manner in which it is made, should not be considered a limitation of the present invention unless specifically set forth in the appended claims.

The opening 22 may be formed by a variety of etching techniques, such as an anisotropic plasma etching process. The dimensions of the opening 22 may be varied as a matter of design choice depending upon the structure ultimately to be formed in the opening 22, e.g., a conductive line or a conductive plug. For example, in the case where a conductive line will be formed in the opening 22, the opening 22 is essentially a trench that may be routed as desired across the surface of the substrate. In situations where a conductive contact or via will be formed in the opening 22, the opening 22 may have a circular, square, or rectangular cross-sectional configuration when viewed from the top. Moreover, irrespective of its shape, e.g., circular, rectangular, etc., the opening 22 should be understood to be defined by a plurality of sidewalls 24. Thus, the particular size, shape or configuration of the opening 22 should not be considered a limitation unless it is specifically set forth in the appended claims.

Next, as shown in Figure 2A, a barrier layer 26 is conformally deposited above the surface 25 of the insulating layer 20 and in the opening 22. It may be formed by a variety of processes, e.g., PVD, CVD, etc. The barrier layer 26 also substantially covers the sidewalls 24 of the opening 22, as shown in Figure 2A. The barrier layer 26 may be formed from a variety of materials, e.g., tantalum, titanium, titanium nitride, tantalum nitride, etc. In certain situations, although not depicted in Figure 2A, the barrier layer 26 may actually be comprised of a bi- layer combination of materials, e.g, a titanium/titanium nitride bi-layer.

The thickness of the barrier layer 26, as well as the manner in which it is formed, are matters of design choice. For example, in situations where the barrier layer 26 is comprised of tantalum, it may have a thickness ranging from approximately 2.5-6 nm (250-600 A), and it may be formed by a PVD process. In view of the foregoing, it is readily apparent that the thickness, the materials of construction, and the manner in which the barrier layer 26 is formed, should not be considered a limitation of the present invention unless specifically recited in the appended claims. ^■ ■ '

Next, as shown in Figure 2B, a layer of conductive material 30 is formed above the surface 27 of the barrier layer 26 and in the opening 22. The conductive material 30 may be comprised of a variety of materials, e.g., copper, tantalum, tungsten, aluminum, etc. In the case where the conductive material 30 is comprised of copper, prior to its formation, a copper seed layer (not shown) may be formed above the surface 27 of the barrier layer 26 and in the opening 22. Thereafter, using known electroplating techniques, the conductive layer 30 comprised of copper may be formed above the structure depicted in Figure 2A. For example, after formation of a copper seed layer, having a thickness ranging from approximately 10-20 nm (1000-2000 A), the structure may be submerged in an inorganic electrolytic bath consisting of copper sulfate, an acid, such as sulfuric acid, and an inorganic anion, such as chloride. Thereafter, an electric current is uniformly applied across the wafer to begin the plating process. Organic compounds may also be added to the bath to enhance uniformity. However, the particular process parameters of the electroplating process should not be considered a limitation of the present invention unless they are specifically set forth in the appended claims.

In situations where the conductive layer 30 is comprised of another material, e.g, tungsten, the layer of conductive material 30 may be directly deposited above the surface 27 of the barrier layer 26 and in the opening 22. Such a layer may be formed by a variety of known processes, e.g., CVD, PVD, etc. Additionally, although not depicted in the drawings, prior to the formation of the conductive layer 30, a layer of adhesion material (not shown), comprised of, for example, titanium nitride, titanium, etc., may be formed above the surface 27 of the barrier layer 26 and in the opening 22.

Thereafter, one or more chemical mechanical polishing ("CMP") operations are performed to remove portions of the conductive layer 30 lying outside of the opening 22 and above the surface 27 of the barrier layer 26. That is, CMP operations are performed until such time that substantially all of the conductive material, e.g., copper, tungsten, is removed from above the surface 27 of the barrier layer 26, thereby exposing the barrier layer 26 to further processing steps as described below. When CMP operations are completed, a surface 31 of the conductive layer 30 is approximately planar with the surface 27 of the barrier layer 26.

Thereafter, an etching process, such as a dry etching process or a sputter etching process, is performed to remove substantially all of the portions of the barrier layer 26 positioned outside the opening 22 and above the surface 25 of the insulating layer 20. This results in the structure depicted in Figure 2D. Note that, through use of this etchback process, substantially all of the barrier layer 26 positioned above the surface 25 of the insulating layer 20 is removed without subjecting the insulating layer 20 to a CMP operation to remove the barrier layer 26. Thus, the insulating layer 20 is not subjected to the large shear forces inherent in such CMP operations.

Thereafter, if deemed necessary, one or more chemical mechanical polishing ("CMP") operations are performed to remove portions of the conductive layer 30 lying outside of the opening 22 above the surface 25 of the insulating layer 20 to define a conductive interconnection 32. That is, CMP operations may be performed until such time that substantially all of the conductive material, e.g., copper, tungsten, is removed from above the surface 25 of the insulating layer 20. When CMP operations are completed, a surface 31A of the conductive interconnection 32 is approximately planar with the surface 25 of the insulating layer 20. This last CMP operation may not be required depending upon how much of the conductive layer 30, e.g., copper, is left and/or how planar the conductive layer 30 is.

In one illustrative embodiment, the method disclosed herein is comprised of forming a layer of insulating material 20, forming an opening 22 in the layer of insulating material 20, and forming a barrier layer 26 above an upper surface 25 of the insulating layer 20 and in the opening 22. The method further comprises forming a conductive material 30 above the upper surface 25 of the barrier layer 20 and in the opening 22, performing a CMP process to remove substantially all of the conductive material 30 positioned above an upper surface 27 of the barrier layer 26 and performing at least one etching process on the barrier layer 26 to remove substantially all of the barrier layer 26 positioned above the upper surface 25 of the insulating layer 20. In some cases, the method further comprises performing at least one chemical mechanical polishing operation to remove at least a portion of the conductive material 30 positioned outside of the opening 22 and above the upper surface 25 of the insulating layer 20 to define a conductive interconnection 32 positioned within the opening 22 in the insulating layer 20.

As shown above, through use of the present invention, conductive interconnections may be formed in an integrated circuit device without performing the CMP operation that is traditionally used to remove the barrier layer from above the surface of the insulating layer. Through use of the present invention, damage to the insulating layer resulting from the CMP process used to remove the barrier layer may be reduced or avoided. As a result, integrated circuit devices may be formed wherein the integrity of the insulating layer is maintained throughout the process of forming conductive interconnections.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.

Claims

1. A method of forming a conductive interconnection, comprising: forming a layer of insulating material 20, said layer having an upper surface 25; forming an opening 22 in said layer of insulating material 20; forming a barrier layer 26 above said upper surface 25 of said insulating layer 20 and in said opening, said barrier layer 26 having an upper surface 27; forming a conductive material above said upper surface 27 of said barrier layer 26 and in said opening 22; performing a chemical mechanical polishing operation to remove substantially all of said conductive material positioned above said upper surface 27 of said barrier layer 26; and performing at least one dry etching process on said barrier layer 26 to remove substantially all of said barrier layer 26 positioned above said upper surface 25 of said insulating layer 20.

2. The method of claim 1, further comprising performing at least one chemical mechanical polishing operation to remove at least a portion of the conductive material positioned outside of said opening 20 and above said upper surface 25 of said insulating layer 20.

3. The method of claim 1, wherein forming a layer of insulating material 20, said layer having an upper surface 25, comprises forming a layer of insulating material 20 comprised of at least one of an oxide, an oxynitride, silicon dioxide, silicon oxynitride, a fluorinated oxide, and an insulating material having a dielectric constant less than approximately 4, said layer having an upper surface 25.

4. The method of claim 1, wherein forming a layer of insulating material 20, said layer having an upper surface 25, comprises forming a layer of insulating material 20 by performing at least one of a deposition process and a thermal growth process, said layer having an upper surface 25.

5. The method of claim 1, wherein forming an opening 22 in said layer of insulating material 20 comprises forming an opening 22 in said layer of insulating material 20 by performing an anisotropic etching process.

6. The method of claim 1, wherein forming an opening 22 in said layer of insulating material 20 comprises forming an opening 22 in said layer of insulating material 20, said opening 22 having a substantially circular, rectangular, or square cross-sectional configuration.

7. The method of claim 1, wherein forming a barrier layer 26 above said upper surface 25 of said insulating layer 20 and in said opening 22 comprises depositing a barrier layer 26 above said upper surface 25 of said insulating layer 20 and in said opening 22.

8. The method of claim 1, wherein forming a barrier layer 26 above said upper surface 25 of said insulating layer 20 and in said opening 22 comprises forming a barrier layer 26 comprised of at least one of tantalum, titanium, titanium nitride and tantalum nitride above said upper surface 25 of said insulating layer 20 and in said opening 22.

9. The method of claim 1, wherein performing at least one dry etching process on said barrier layer 26 to remove substantially all of said barrier layer 26 positioned above said upper surface 25 of said insulating layer 20 comprises performing at least one sputter etching process on said barrier layer 26 to remove substantially all of said barrier layer 26 positioned above said upper surface 25 of said insulating layer 20.

10. The method of claim 1, wherein forming a conductive material above said upper surface 27 of said barrier layer 26 and in said opening 22 comprises forming a conductive material comprised of at least one of copper, tungsten, and aluminum above said upper surface 27 of said barrier layer 26 and in said opening 22.

11. The method of claim 1, wherein forming a conductive material above said upper surface 27 of said barrier layer 26 and in said opening 22 comprises: forming a copper seed layer above said upper surface 27 of said barrier layer 26 and in said opening 22; and performing an electroplating operation to form a conductive material comprised of copper above said upper surface of said barrier layer and in said opening.

12. The method of claim 1, wherein forming a conductive material above said upper surface 27 of said barrier layer 26 and in said opening 22 comprises depositing a layer of conductive material comprised of at least one of copper, tungsten, and aluminum above said upper surface 27 of said barrier layer 26 and in said opening 22.

13. The method of claim 1, wherein said conductive interconnection is comprised of a conductive line or a conductive plug.

14. A method of forming a conductive interconnection, comprising: depositing a layer of insulating material 20, said layer having an upper surface 25; etching an opening 22 in said layer of insulating material 20; depositing a barrier layer 26 above said upper surface 25 of said insulating layer 20 and in said opening

22, said barrier layer 26 having an upper surface 27; forming a conductive material above said upper surface 27 of said barrier layer 26 and in said opening 22; performing a chemical mechanical polishing operation to remove substantially all of said conductive material positioned above said upper surface 27 of said barrier layer 26; and performing at least one dry etching process on said barrier layer 26 to remove substantially all of said barrier layer 26 positioned above said upper surface 25 of said insulating layer 20.

15. A method, comprising: forming a layer of insulating material 20, said layer having an upper surface 25; forming an opening 22 in said layer of insulating material 20; forming a barrier layer 26 comprised of tantalum above said upper surface 25 of said insulating layer 20 and in said opening 22, said barrier layer 26 having an upper surface 27; forming a conductive material comprised of copper above said upper surface 27 of said barrier layer 26 and in said opening 22; performing a chemical mechanical polishing operation to remove substantially all of said conductive material positioned above said upper surface 27 of said barrier layer 26; and performing at least one dry etching process on said barrier layer 26 to remove substantially all of said barrier layer 26 positioned above said upper surface 25 of said insulating layer 20.