AU2001275273A1 - Method of forming copper interconnect capping layers with improved interface andadhesion - Google Patents

Method of forming copper interconnect capping layers with improved interface andadhesion

Info

Publication number
AU2001275273A1
AU2001275273A1 AU2001275273A AU7527301A AU2001275273A1 AU 2001275273 A1 AU2001275273 A1 AU 2001275273A1 AU 2001275273 A AU2001275273 A AU 2001275273A AU 7527301 A AU7527301 A AU 7527301A AU 2001275273 A1 AU2001275273 A1 AU 2001275273A1
Authority
AU
Australia
Prior art keywords
andadhesion
copper interconnect
capping layers
forming copper
improved interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001275273A
Inventor
Joerg Hohage
Richard Huang
Robert A. Huertas
Lothar Mergili
Minh Van Ngo
Hartmut Ruelke
Lu You
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001275273A1 publication Critical patent/AU2001275273A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/913—Diverse treatments performed in unitary chamber

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
AU2001275273A 2000-07-26 2001-06-04 Method of forming copper interconnect capping layers with improved interface andadhesion Abandoned AU2001275273A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/626,455 US6596631B1 (en) 2000-07-26 2000-07-26 Method of forming copper interconnect capping layers with improved interface and adhesion
US09626455 2000-07-26
PCT/US2001/018228 WO2002009173A2 (en) 2000-07-26 2001-06-04 Method of forming copper interconnect capping layers with improved interface and adhesion

Publications (1)

Publication Number Publication Date
AU2001275273A1 true AU2001275273A1 (en) 2002-02-05

Family

ID=24510446

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001275273A Abandoned AU2001275273A1 (en) 2000-07-26 2001-06-04 Method of forming copper interconnect capping layers with improved interface andadhesion

Country Status (9)

Country Link
US (1) US6596631B1 (en)
EP (1) EP1303876B1 (en)
JP (1) JP2004505447A (en)
KR (1) KR100774599B1 (en)
CN (1) CN1276498C (en)
AU (1) AU2001275273A1 (en)
DE (1) DE60139695D1 (en)
TW (1) TW512491B (en)
WO (1) WO2002009173A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3705724B2 (en) * 1999-11-19 2005-10-12 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of semiconductor device
DE10059143B4 (en) 2000-11-29 2006-12-28 Advanced Micro Devices, Inc., Sunnyvale Surface treatment and cover layer method for producing a copper interface in a semiconductor device
US20090004850A1 (en) 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
DE10150822B4 (en) * 2001-10-15 2007-01-25 Advanced Micro Devices, Inc., Sunnyvale Method for removing oxidized areas on a surface of a metal surface
US6977218B2 (en) * 2003-07-17 2005-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating copper interconnects
KR101044611B1 (en) * 2004-06-25 2011-06-29 매그나칩 반도체 유한회사 Method of forming a metal line in a semiconductor device
JP4516447B2 (en) 2005-02-24 2010-08-04 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US7534732B1 (en) 2006-02-17 2009-05-19 Spansion Llc Semiconductor devices with copper interconnects and composite silicon nitride capping layers
US7713866B2 (en) * 2006-11-21 2010-05-11 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
JP2009141058A (en) 2007-12-05 2009-06-25 Fujitsu Microelectronics Ltd Semiconductor device and method of manufacturing the same
CN102263056A (en) * 2010-05-26 2011-11-30 中芯国际集成电路制造(上海)有限公司 Metal interconnection method
CN102446833B (en) * 2011-09-29 2015-04-29 上海华力微电子有限公司 Processing method for reducing particles of dual-damascene silicon nitride process
US9269612B2 (en) * 2011-11-22 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of forming damascene interconnect structures
SG11201407282XA (en) * 2012-07-31 2015-01-29 Univ Nanyang Tech Semiconductor device and method for forming the same
CN104157603B (en) * 2013-05-15 2017-02-08 中芯国际集成电路制造(上海)有限公司 Method for enhancing combination strength of metal copper and NDC interface
JP2020043263A (en) * 2018-09-12 2020-03-19 キオクシア株式会社 Semiconductor device and method for manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6174810B1 (en) * 1998-04-06 2001-01-16 Motorola, Inc. Copper interconnect structure and method of formation
US6242347B1 (en) * 1998-09-30 2001-06-05 Applied Materials, Inc. Method for cleaning a process chamber
US20010049181A1 (en) * 1998-11-17 2001-12-06 Sudha Rathi Plasma treatment for cooper oxide reduction
US6225210B1 (en) * 1998-12-09 2001-05-01 Advanced Micro Devices, Inc. High density capping layers with improved adhesion to copper interconnects
US6153523A (en) * 1998-12-09 2000-11-28 Advanced Micro Devices, Inc. Method of forming high density capping layers for copper interconnects with improved adhesion
US6271595B1 (en) * 1999-01-14 2001-08-07 International Business Machines Corporation Method for improving adhesion to copper

Also Published As

Publication number Publication date
TW512491B (en) 2002-12-01
WO2002009173A2 (en) 2002-01-31
WO2002009173A3 (en) 2002-05-23
KR100774599B1 (en) 2007-11-09
EP1303876B1 (en) 2009-08-26
EP1303876A2 (en) 2003-04-23
JP2004505447A (en) 2004-02-19
KR20030020415A (en) 2003-03-08
US6596631B1 (en) 2003-07-22
CN1276498C (en) 2006-09-20
DE60139695D1 (en) 2009-10-08
CN1552096A (en) 2004-12-01

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