JP2006324414A - 半導体装置及びその製造方法 - Google Patents
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- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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Abstract
【解決手段】上記の課題を解決した半導体装置は、配線溝若しくは接続孔の少なくとも一方が形成され、配線溝若しくは接続孔表面近傍の炭素濃度若しくは膜密度が内部の炭素濃度若しくは膜密度と同等若しくはそれより高い低誘電率絶縁膜と、前記配線溝若しくは接続孔内に形成された導電体層と、前記低誘電率絶縁膜と前記導電体層との間に設けられたバリアメタルと、前記バリアメタルと前記低誘電率絶縁膜との間に設けられた第2の絶縁膜とを具備する配線構造を具備する。
【選択図】図1
Description
本発明の第1の実施形態による半導体装置の断面構造の一例を図1に示す。本実施形態の半導体装置は、半導体基板10の上方に形成された第2の層間絶縁膜210に配線用溝及ビアホールを形成した際に、加工された第2の層間絶縁膜210の表面に導入されたダメージ層を有機材料を用いて回復させて回復層210Rにした後で、第2の絶縁膜215、第2のバリアメタル220を介してビアプラグ225及び第2の配線230を形成したものである。
本発明の第2の実施形態は、ビアホール225h底部の第1の配線130上の第1の拡散防止膜205を除去した後で、第2の層間絶縁膜210のエッチングにより導入されたダメージを回復させることによって、ビア及び配線の信頼性を向上させた半導体装置である。本実施形態によれば、第2の配線溝230t底部に導入されるダメージを、第1の実施形態よりも低減できる。
本発明の第3の実施形態は、配線の信頼性劣化で最も問題になる部分の一つであるビアホール部のダメージ回復を行った半導体装置及びその製造方法である。すなわち、低誘電率層間絶縁膜中に初めにビアホールのみを形成し、ビアホール周囲の層間絶縁膜中に導入されたダメージ層を回復させた後で、配線溝を形成するものである。
本発明の第4の実施形態は、第3の実施形態と同様に配線の信頼性劣化で最も問題になる部分の一つであるビアホール部のダメージ回復を行った半導体装置及びその製造方法であるが、配線溝を形成した後で、水分の拡散を防止する機能を有する第2の絶縁膜を形成する。
上記の実施形態は、いずれも配線上を含む配線を形成した絶縁膜上の全面に拡散防止膜を形成した構造を例に、説明してきた。本発明は、配線金属の上面にだけ拡散防止膜を形成した、いわゆる、キャップメタル若しくはトップバリアメタルと呼ばれる構造(以下、キャップメタル構造と呼ぶ)にも適用することができる。
上記の実施形態及び変形例は、層間絶縁膜中に形成したビアホールと配線溝に同時にバリアメタル及び金属を埋め込んだデュアルダマシン構造を例に説明してきた。しかし、本発明は、ビアホールと配線溝にそれぞれ別のプロセスで個々にバリアメタル及び金属を埋め込むシングルダマシン構造に対しても適用することができる。
Claims (5)
- 配線溝若しくは接続孔の少なくとも一方が形成され、配線溝若しくは接続孔表面近傍の炭素濃度若しくは膜密度が内部の炭素濃度若しくは膜密度と同等若しくはそれより高い低誘電率絶縁膜と、
前記配線溝若しくは接続孔内に形成された導電体層と、
前記低誘電率絶縁膜と前記導電体層との間に設けられたバリアメタルと、
前記バリアメタルと前記低誘電率絶縁膜との間に設けられた第2の絶縁膜と
を具備する配線構造を具備することを特徴とする半導体装置。 - 前記低誘電率絶縁膜は、比誘電率が2.5以下であることを特徴とする請求項1に記載の半導体装置。
- 前記第2の絶縁膜は、シリコンと少なくとも炭素若しくは窒素のいずれかを含むことを特徴とする請求項1若しくは2に記載の半導体装置。
- 前記第2の絶縁膜を形成することによる前記接続孔における前記導電体層の抵抗上昇率が、20%以下であることを特徴とする請求項1ないし3のいずれか1に記載の半導体装置。
- 半導体基板の上方に低誘電率絶縁膜を堆積する工程と、
前記低誘電率絶縁膜中に配線溝若しくは接続孔の少なくとも一方を形成する工程と、
前記形成する工程において前記配線溝表面若しくは接続孔表面近傍の前記低誘電率絶縁膜中に導入されたダメージを回復させる工程と、
前記配線溝若しくは接続孔表面に第2の絶縁膜を形成する工程と、
前記第2の絶縁膜上にバリアメタルを形成する工程と、
前記配線溝若しくは接続孔内に導電体層を形成する工程と
を具備することを特徴とする半導体装置の製造方法。
Priority Applications (2)
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JP2005145575A JP2006324414A (ja) | 2005-05-18 | 2005-05-18 | 半導体装置及びその製造方法 |
US11/248,608 US20060261483A1 (en) | 2005-05-18 | 2005-10-13 | Semiconductor device and method for manufacturing the same |
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JP2005145575A JP2006324414A (ja) | 2005-05-18 | 2005-05-18 | 半導体装置及びその製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008159720A (ja) * | 2006-12-21 | 2008-07-10 | Nec Electronics Corp | 半導体装置並びに半導体装置の製造方法 |
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JP2007027436A (ja) * | 2005-07-15 | 2007-02-01 | Toshiba Corp | 半導体装置およびその製造方法 |
US7749896B2 (en) * | 2005-08-23 | 2010-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for forming the same |
JP2007067066A (ja) * | 2005-08-30 | 2007-03-15 | Toshiba Corp | 半導体装置とその製造方法 |
US20070126120A1 (en) * | 2005-12-06 | 2007-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
JP2007234719A (ja) * | 2006-02-28 | 2007-09-13 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP4741965B2 (ja) * | 2006-03-23 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7329956B1 (en) * | 2006-09-12 | 2008-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene cleaning method |
US7846841B2 (en) | 2008-09-30 | 2010-12-07 | Tokyo Electron Limited | Method for forming cobalt nitride cap layers |
US8536707B2 (en) * | 2011-11-29 | 2013-09-17 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor structure comprising moisture barrier and conductive redistribution layer |
KR102616489B1 (ko) | 2016-10-11 | 2023-12-20 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
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