JP2007227507A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- JP2007227507A JP2007227507A JP2006044906A JP2006044906A JP2007227507A JP 2007227507 A JP2007227507 A JP 2007227507A JP 2006044906 A JP2006044906 A JP 2006044906A JP 2006044906 A JP2006044906 A JP 2006044906A JP 2007227507 A JP2007227507 A JP 2007227507A
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Abstract
【解決手段】例えば、UDC拡散バリア膜22、ポーラスシリカ膜23、UDCミドルストッパ膜24、ポーラスシリカ膜25およびUDC拡散バリア膜26の積層構造にビア溝27aと配線溝27bを形成したときに、内部に露出するUDC拡散バリア膜22、UDCミドルストッパ膜24、UDC拡散バリア膜26の表面に対し、水素プラズマを照射する。これにより、各SiC膜の露出表面をSiリッチにする。そして、プラズマ照射後のビア溝27aと配線溝27bにTa膜28を形成し、Cuで埋め込む。Ta膜28と接触することとなるSiC膜の表面をあらかじめSiリッチな状態にしておくことにより、Ta膜28をCuの突き抜けが抑えられるような結晶構造に制御することが可能になる。これにより、配線からのCuの拡散を防止することが可能になる。
【選択図】図7
Description
まず、UDCを拡散バリア膜に用いたときのCuの拡散現象について説明する。
図1はCuの拡散現象の説明図である。この図1には、ダマシン法を用いて形成された多層配線構造の一例の要部断面を模式的に図示している。
図2には、比誘電率の異なる3種類のUDC膜上にそれぞれTa膜を膜厚18nmで成膜したサンプル(図中、「UDC」と表示。)、および比誘電率の異なる3種類のODC膜上にそれぞれTa膜を膜厚18nmで成膜したサンプル(図中、「ODC」と表示。)について、それぞれTa膜の複数箇所のシート抵抗を測定し、そのシート抵抗を示す箇所の存在確率を求めた結果を示している。また、図2には、Si膜上にTa膜を膜厚18nmで成膜したサンプル(図中、「Si」と表示。)のTa膜のシート抵抗と存在確率の関係も併せて示している。
図3はSiC膜上に成膜されたTa膜の結晶構造の解析結果を示す図である。Ta膜の結晶構造解析にはX線回折(X-Ray Diffraction,XRD)装置を用いた。図3において、横軸は回折角2θ(deg)を表し、縦軸は回折X線の強度(cps(counts/sec))を表している。なお、図3には、Si膜上に成膜されたTa膜の結晶構造の解析結果も併せて図示している。
図4はSiC膜のC含有量とTa膜の結晶性の関係を示す図である。図4において、横軸は上記図3の解析に用いたサンプルのUDC,ODC膜のC含有量(atom%)を表し、縦軸は上記図3で得られたα−Taの回折X線の強度(cps)を表している。
図5は水素プラズマ処理を行ったSiC膜上に成膜されたTa膜のシート抵抗の測定結果を示す図である。図5において、横軸はTa膜のシート抵抗(Ω/□)を表し、縦軸は確率(%)を表している。
まず、第1の適用例について説明する。
シリコン基板10の素子分離領域11で画定された素子領域内に、常法に従い、ゲート絶縁膜12a、ゲート電極12b、サイドウォール12cおよび不純物拡散領域12d,12eを有する絶縁ゲート型のトランジスタ12を形成した。
次いで、UDC拡散バリア膜22上に、NCSを用いてハイブリッド型のポーラスシリカ膜23をスピンオンプロセスにより膜厚約200nmで成膜した。その後、UDC膜をCVD法により成膜してUDCミドルストッパ膜24を形成し、UDCミドルストッパ膜24上に、NCSを用いてハイブリッド型のポーラスシリカ膜25をスピンオンプロセスにより膜厚約170nmで成膜した。そして、その上に膜厚約50nmのUDC膜をCVD法により成膜し、UDC拡散バリア膜26を形成した。なお、その形成条件は、先に形成したUDC拡散バリア膜22の形成時と同じにした。
この2層目の配線層の上には、まず、SiO2層間絶縁膜31を形成して、そこに配線溝を形成し、さらに、Ta膜32およびCu膜33を成膜して、Cuを埋め込み、CMPを行ってCu配線34を形成した。そして、その表面にUDC拡散バリア膜35およびSiO2層間絶縁膜36を形成し、UDC拡散バリア膜35をエッチングストッパにして最終的にCu配線34に通じるビア溝を形成した。そして、そこにWプラグ37を形成し、さらにその上にアルミニウム(Al)パッド38を形成し、最後に、Alパッド38表面の一部を残してその他の領域に保護膜39を形成した。
また、この第1の適用例の多層配線構造とは別に、ここでは比較例として、上記のプロセスのうち、1層目の配線溝18a,18bの形成後とビア溝27aおよび2層目の配線溝27bの形成後に行った水素プラズマ処理のプロセスを省略し、それ以外のプロセスおよび構成は同じにした多層配線構造も併せて形成した。
(付記1) 多層配線を有する半導体装置の製造方法において、
SiC膜と絶縁膜の積層構造を形成する工程と、
前記積層構造に溝を形成する工程と、
前記溝を形成したときに前記溝の内部に露出する前記SiC膜の表面をSiリッチにする工程と、
前記溝にバリアメタルを形成する工程と、
前記バリアメタルが形成された前記溝を導電材料で埋め込む工程と、
を有することを特徴とする半導体装置の製造方法。
前記表面に対して水素を含有するプラズマを照射することによって、前記表面をSiリッチにすることを特徴とする付記1記載の半導体装置の製造方法。
前記表面に対してアンモニアを含有するプラズマを照射することによって、前記表面をSiリッチにすることを特徴とする付記1記載の半導体装置の製造方法。
前記表面に対して窒素を含有するプラズマを照射することによって、前記表面をSiリッチにすることを特徴とする付記1記載の半導体装置の製造方法。
前記表面に対して紫外線を照射することによって、前記表面をSiリッチにすることを特徴とする付記1記載の半導体装置の製造方法。
前記表面にSi層を形成することによって、前記表面をSiリッチにすることを特徴とする付記1記載の半導体装置の製造方法。
前記SiC膜を、原料にオルガノシランを用い低酸素濃度または酸素を含まない雰囲気下で気相成長させることによって形成することを特徴とする付記1記載の半導体装置の製造方法。
上層側がSiリッチになるような組成勾配を有するSiC膜と絶縁膜の積層構造を形成する工程と、
前記積層構造に内部に前記SiC膜が露出する溝を形成する工程と、
前記溝にバリアメタルを形成する工程と、
前記バリアメタルが形成された前記溝を導電材料で埋め込む工程と、
を有することを特徴とする半導体装置の製造方法。
前記SiC膜の形成の間、前記SiC膜の原料の濃度を制御することによって、表面がSiリッチになるような組成勾配を有する前記SiC膜を形成することを特徴とする付記9記載の半導体装置の製造方法。
(付記12) 前記積層構造に前記SiC膜が露出する前記溝を形成する工程後に、
前記溝を形成したときに前記溝内に露出する前記SiC膜の表面をSiリッチにする工程を有することを特徴とする付記9記載の半導体装置の製造方法。
SiC膜と絶縁膜の積層構造と、
前記積層構造に形成され内部に前記SiC膜が露出する溝と、
前記溝に形成されたバリアメタルと、
前記バリアメタルが形成された前記溝に埋め込まれた導電材料と、
を有し、
前記SiC膜は、前記バリアメタルとの接触面がSiリッチになっていることを特徴とする半導体装置。
(付記17) 前記SiC膜は、比誘電率が2.5〜4.5の範囲であることを特徴とする付記14記載の半導体装置。
2,6 UDC膜
3a,3b,7,19,28,32 Ta膜
4a,4b,8b,21a,21b,30b,34 Cu配線
8a,30a Cuビア
10 シリコン基板
11 素子分離領域
12 トランジスタ
12a ゲート絶縁膜
12b ゲート電極
12c サイドウォール
12d,12e 不純物拡散領域
13 PSG
14a,14b,37 Wプラグ
15 UDCエッチングストッパ膜
16,23,25 ポーラスシリカ膜
17 SiOキャップ膜
18a,18b,27b 配線溝
20,29,33 Cu膜
22,26,35 UDC拡散バリア膜
24 UDCミドルストッパ膜
27a ビア溝
31,36 SiO2層間絶縁膜
38 Alパッド
39 保護膜
Claims (8)
- 多層配線を有する半導体装置の製造方法において、
SiC膜と絶縁膜の積層構造を形成する工程と、
前記積層構造に溝を形成する工程と、
前記溝を形成したときに前記溝の内部に露出する前記SiC膜の表面をSiリッチにする工程と、
前記溝にバリアメタルを形成する工程と、
前記バリアメタルが形成された前記溝を導電材料で埋め込む工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記溝を形成したときに前記溝内に露出する前記SiC膜の前記表面をSiリッチにする工程においては、
前記表面に対して水素、アンモニア、又は窒素のいずれかを含有するプラズマを照射することによって、前記表面をSiリッチにすることを特徴とする請求項1記載の半導体装置の製造方法。 - 前記溝を形成したときに前記溝内に露出する前記SiC膜の前記表面をSiリッチにする工程においては、
前記表面に対して紫外線を照射することによって、前記表面をSiリッチにすることを特徴とする請求項1記載の半導体装置の製造方法。 - 前記溝を形成したときに前記溝内に露出する前記SiC膜の前記表面をSiリッチにする工程においては、
前記表面にSi層を形成することによって、前記表面をSiリッチにすることを特徴とする請求項1記載の半導体装置の製造方法。 - 多層配線を有する半導体装置の製造方法において、
上層側がSiリッチになるような組成勾配を有するSiC膜と絶縁膜の積層構造を形成する工程と、
前記積層構造に内部に前記SiC膜が露出する溝を形成する工程と、
前記溝にバリアメタルを形成する工程と、
前記バリアメタルが形成された前記溝を導電材料で埋め込む工程と、
を有することを特徴とする半導体装置の製造方法。 - 上層側がSiリッチになるような組成勾配を有する前記SiC膜と前記絶縁膜の積層構造を形成する工程においては、
前記SiC膜の形成の間、前記SiC膜の原料の濃度を制御することによって、表面がSiリッチになるような組成勾配を有する前記SiC膜を形成することを特徴とする請求項5記載の半導体装置の製造方法。 - 多層配線を有する半導体装置において、
SiC膜と絶縁膜の積層構造と、
前記積層構造に形成され内部に前記SiC膜が露出する溝と、
前記溝に形成されたバリアメタルと、
前記バリアメタルが形成された前記溝に埋め込まれた導電材料と、
を有し、
前記SiC膜は、前記バリアメタルとの接触面がSiリッチになっていることを特徴とする半導体装置。 - 前記バリアメタルは、Ta,TaN,Ti,TiN,W,WN,Zr,ZrN,V,VN,TiZr,TiZrNのうちの1種または2種以上を含むことを特徴とする請求項7記載の半導体装置。
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