JP4335932B2 - 半導体装置製造およびその製造方法 - Google Patents
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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Description
TμCR
で表される性質を示す。
C=εS/D
として表される。
1.銅配線、当該銅配線に直接接する特定絶縁層、当該特定絶縁層に直接接する特定炭素膜、当該特定炭素膜に直接接する特定ポーラス絶縁層、当該特定ポーラス絶縁層に直接接する導電性または絶縁性のバリア層、当該導電性または絶縁性のバリア層に直接接する銅配線をこの順に有する積層構造
2.銅配線、当該銅配線に直接接する導電性または絶縁性のバリア層、当該導電性または絶縁性のバリア層に直接接する特定ポーラス絶縁層、当該特定ポーラス絶縁層に直接接する特定炭素膜、当該特定炭素膜に直接接する特定絶縁層、当該特定絶縁層に直接接する銅配線をこの順に有する積層構造
3.銅配線、当該銅配線に直接接する特定絶縁層、当該特定絶縁層に直接接する特定炭素膜、当該特定炭素膜に直接接する特定ポーラス絶縁層、当該特定ポーラス絶縁層に直接接する特定炭素膜、当該特定炭素膜に直接接する特定絶縁層、当該特定絶縁層に直接接する銅配線をこの順に有する積層構造を例示することができる。
熱酸化したSiウエハ上にスパッタリング法によって銅膜を40nm製膜し、その上に平行平板プラズマCVD装置によって、各種の特定絶縁層(SiO絶縁膜、SiC絶縁膜、SiOC絶縁膜、SiN絶縁膜、SiON絶縁膜およびSiOCN絶縁膜、ただしいずれも水素が共存している)を製膜した。特定絶縁層の厚さは成膜時間を変化させることで調整した。なお、本明細書において、Si:O:C:Hとは、水素が共存するSiOC絶縁膜を示し、Si:O:N:Hとは、水素が共存するSiON絶縁膜を示し、Si:C:Hとは、水素が共存するSiC絶縁膜を示し、Si:O:Hとは、水素が共存するSiO絶縁膜を示し、Si:N:Hとは、水素が共存するSiN絶縁膜を示し、Si:O:C:N:Hとは、水素が共存するSiOCN絶縁膜を示す。
実施例1と同様な構造の積層体を特定絶縁層厚:1.5nm、特定炭素膜厚:9nmとして作製した。成膜条件は上記と同じである。その後、温度を変えて真空中で2分間の加熱処理を実施し、サンプルを準備した。
多層積層体を作製した場合における特定絶縁層挿入の効果をみるため、図4に示す積層体を作製した。このとき、繰り返し単位の総数は6である。
「銅配線、当該銅配線に直接接するケイ素系絶縁層、当該ケイ素系絶縁層に直接接するバリア層、当該バリア層に直接接する酸化ケイ素系ポーラス絶縁層、当該ケイ素系ポーラス絶縁層に直接接するバリア層、当該バリア層に直接接する銅配線をこの順に有する積層構造」を用いて作製した半導体集積回路の断面を概略的に図6に示す。
本例は、「銅配線、当該銅配線に直接接するケイ素系絶縁層、当該ケイ素系絶縁層に直接接するバリア層、当該バリア層に直接接する酸化ケイ素系ポーラス絶縁層、当該ケイ素系ポーラス絶縁層に直接接するバリア層、当該バリア層に直接接するケイ素系絶縁層、当該ケイ素系絶縁層に直接接する銅配線をこの順に有する積層構造」を用いて作製した半導体集積回路に関するものである。
当該半導体装置が、銅配線、バリア層、当該バリア層に直接接する酸化ケイ素系ポーラス絶縁層、当該ケイ素系ポーラス絶縁層に直接接するバリア層、銅配線をこの順に有する積層構造を少なくとも一つ有し、
当該バリア層の少なくとも一つが密度2.4g/cm3以上のアモルファス炭素膜であり、
当該アモルファス炭素膜と銅配線との間にこれらに直接接するケイ素系絶縁層が存在する、
半導体装置。
当該バリア層が両方とも密度2.4g/cm3以上のアモルファス炭素膜である、
付記1〜6のいずれかに記載の半導体装置。
当該ケイ素系絶縁層に直接接するバリア層が密度2.4g/cm3以上のアモルファス炭素膜である、
付記1〜6のいずれかに記載の半導体装置。
Claims (9)
- 銅配線層を有する半導体装置において、
当該半導体装置が、銅配線、バリア層、当該バリア層に直接接する酸化ケイ素系ポーラス絶縁層、当該ケイ素系ポーラス絶縁層に直接接するバリア層、銅配線をこの順に有する積層構造を少なくとも一つ有し、
当該バリア層の少なくとも一つが密度2.4g/cm3以上のアモルファス炭素膜であり、
当該アモルファス炭素膜と銅配線との間にこれらに直接接し、水素が共存している、SiO,SiC,SiOC,SiN,SiONおよびSiOCNのうちのいずれかからなるケイ素系絶縁層が存在する、
半導体装置。 - 前記ケイ素系絶縁層の厚さが1〜8nmの範囲にあり、かつ、前記アモルファス炭素膜の厚さが1〜10nmの範囲にある、請求項1に記載の半導体装置。
- 前記酸化ケイ素系ポーラス絶縁層の比誘電率が2.4以下である、請求項1または2に記載の半導体装置。
- 前記半導体装置が多層配線構造を有し、当該多層配線構造の少なくとも一部に前記積層構造を含む、請求項1〜3のいずれかに記載の半導体装置。
- 前記半導体装置が、銅配線、当該銅配線に直接接するケイ素系絶縁層、当該ケイ素系絶縁層に直接接するバリア層、当該バリア層に直接接する酸化ケイ素系ポーラス絶縁層、当該ケイ素系ポーラス絶縁層に直接接するバリア層、当該バリア層に直接接する銅配線をこの順に有する積層構造を少なくとも一つ有し、
当該ケイ素系絶縁層に直接接するバリア層が密度2.4g/cm3以上のアモルファス炭素膜である、
請求項1〜4のいずれかに記載の半導体装置。 - 請求項1〜5のいずれかに記載の半導体装置の製造方法において、銅配線と、当該銅配線に直接接するケイ素系絶縁層と当該ケイ素系絶縁層に直接接する密度2.4g/cm3以上のアモルファス炭素膜との形成後に240℃以上の温度で加熱処理することを含む、半導体装置の製造方法。
- 前記ケイ素系絶縁層がCVD法によって成膜されたものである、請求項6に記載の半導体装置の製造方法。
- 前記アモルファス炭素膜がフィルタードカソーディックアーク法によって製膜された炭素膜である、請求項6または7に記載の半導体装置の製造方法。
- 前記酸化ケイ素系ポーラス絶縁層が、塗布法によって作製されたものである、請求項6〜8のいずれかに記載の半導体装置の製造方法。
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JP2007046959A JP4335932B2 (ja) | 2007-02-27 | 2007-02-27 | 半導体装置製造およびその製造方法 |
US12/038,497 US8513805B2 (en) | 2007-02-27 | 2008-02-27 | Manufacturing of a semiconductor device and the manufacturing method |
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CN103229283B (zh) | 2010-11-26 | 2016-01-20 | 富士通株式会社 | 半导体装置及半导体装置的制造方法 |
JP5866769B2 (ja) * | 2011-02-16 | 2016-02-17 | 富士通株式会社 | 半導体装置、電源装置及び増幅器 |
JP7151976B2 (ja) * | 2018-03-28 | 2022-10-12 | インテル・コーポレーション | 半導体構造の製造のための炭素系誘電体材料および結果として得られる構造 |
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US6531407B1 (en) * | 2000-08-31 | 2003-03-11 | Micron Technology, Inc. | Method, structure and process flow to reduce line-line capacitance with low-K material |
CN101580928B (zh) * | 2003-02-26 | 2012-07-18 | 住友电气工业株式会社 | 无定形碳膜及其制备方法以及无定形碳膜涂敷的材料 |
JP2006024811A (ja) * | 2004-07-09 | 2006-01-26 | Sony Corp | 半導体装置の製造方法 |
JP2006216746A (ja) * | 2005-02-03 | 2006-08-17 | Sony Corp | 半導体装置 |
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