JP2005311366A - 半導体相互接続構造体およびその製造方法 - Google Patents
半導体相互接続構造体およびその製造方法 Download PDFInfo
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Abstract
【解決手段】 本発明の相互接続構造体は(誘電率が4.0未満である)上部低誘電率(low-k)誘電体層(たとえばSi、C、O、およびHから成る元素群を含む誘電体)とその下に存在する拡散障壁キャップ誘電体層(たとえばC、Si、N、およびHから成る元素群を含むキャップ層)との間の接着性が、これら2つの層の間に接着遷移層を設けることにより改善されている。上部低誘電率(low-k)誘電体層と拡散障壁キャップ誘電体層との間に接着遷移層が存在するから、パッケージング工程の間に相互接続構造体が離層する機会を低減させることが可能になる。ここで提供する接着遷移層は下部SiOx (またはSiON)含有領域と上部C傾斜領域とを備えている。このような構造体、特に接着遷移層を形成する方法も提供する。
【選択図】 図2
Description
12 上部CVD低誘電率(low-k)SiCOH誘電体層
14 金属配線領域
16 SiON薄層
18 拡散障壁キャップ誘電体層
20 下部CVD低誘電率(low-k)SiCOH誘電体層
50 相互接続構造体
52 基板
54 下部低誘電率(low-k)誘電体層
56 配線領域
58 拡散障壁層
60 拡散障壁キャップ誘電体層
62 接着遷移層
64 下部SiOx (またはSiON)含有領域
66 上部C傾斜領域
68 上部低誘電率(low-k)誘電体層
Claims (32)
- 少なくとも、
誘電率が4.0未満である上部低誘電率(low-k)誘電体層と、
下に存在るす拡散障壁キャップ誘電体層と
を備えた相互接続構造体であって、
前記上部低誘電率(low-k)誘電体層と前記下に存在るす拡散障壁キャップ誘電体層との間に、下部SiOx (またはSiON)含有領域と上部C傾斜領域とを備えた接着遷移層が設けられている、
相互接続構造体。 - 前記接着遷移層の前記上部C傾斜領域は前記下部SiOx (またはSiON)含有領域の近傍においてCが欠乏している、
請求項1に記載の相互接続構造体。 - 前記拡散障壁キャップ誘電体層は下部低誘電率(low-k)誘電体層の表面に設けられている、
請求項1に記載の相互接続構造体。 - 前記下部低誘電率(low-k)誘電体層は金属配線領域を備えている、
請求項3に記載の相互接続構造体。 - 前記金属配線領域は導電性金属から成る、
請求項4に記載の相互接続構造体。 - 前記導電性金属はAl、Cu、W、または、これらの合金である、
請求項5に記載の相互接続構造体。 - 前記上部低誘電率(low-k)誘電体層は金属配線領域を備えている、
請求項1に記載の相互接続構造体。 - 前記金属配線領域は導電性金属から成る、
請求項7に記載の相互接続構造体。 - 前記導電性金属はAl、Cu、W、または、これらの合金である、
請求項8に記載の相互接続構造体。 - 前記下部SiOx (またはSiON)含有領域の厚さが約1〜約20nmである、
請求項1に記載の相互接続構造体。 - 前記上部C傾斜領域の厚さが約1〜約50nmである、
請求項1に記載の相互接続構造体。 - 前記上部低誘電率(low-k)誘電体層はSi、C、O、およびHから成る元素群を含んでおり、
前記下に存在るす拡散障壁キャップ誘電体層はC、Si、Hから成る元素群を含んでおり、任意事項としてNを含んでいる、
請求項1に記載の相互接続構造体。 - 少なくとも、
Si、C、O、およびHから成る元素群を含む上部低誘電率(low-k)誘電体層と、
C、Si、N、およびHから成る元素群を含む下に存在るす拡散障壁キャップ誘電体層と
を備えた相互接続構造体であって、
前記上部低誘電率(low-k)誘電体層と前記下に存在るす拡散障壁キャップ誘電体層との間に、下部SiOx (またはSiON)含有領域と上部C傾斜領域とを備えた接着遷移層が設けられている、
相互接続構造体。 - 相互接続構造体を形成する方法であって、
拡散障壁キャップ誘電体層の表面に接着遷移層を形成するステップであって、前記接着遷移層は下部SiOx (またはSiON)含有領域と上部C傾斜領域とを備えている、ステップと、
前記接着遷移層の表面に誘電率が4.0未満の低誘電率(low-k)誘電体層を形成するステップであって、前記低誘電率(low-k)誘電体層が前記接着遷移層の前記上部C傾斜領域と接触して界面を形成している、ステップと
を備えた
方法。 - 接着遷移層を形成する前記ステップが、
前記低誘電率(low-k)誘電体層を形成する始めの段階の間に、前記拡散障壁キャップ誘電体層をアルゴン・プラズマによる前処理工程に置くステップ
を備えている、
請求項14に記載の方法。 - 前記アルゴン・プラズマを、任意にN、He、Xe、またはKrとともに使用してよい、Arガスから生成する、
請求項15に記載の方法。 - 前記アルゴン・プラズマによる前処理工程を、6.67〜2666.4Pa(0.05〜20Torr)の動作圧力で、約5〜約60秒間行う、
請求項15に記載の方法。 - 前記アルゴン・プラズマをRF電源を用いて生成する、
請求項15に記載の方法。 - 接着遷移層を形成する前記ステップが、
前記拡散障壁キャップ誘電体層を、当該拡散障壁キャップ誘電体層の上表面領域をSiO含有層に変換する、酸素プラズマによる処理にさらすステップと、
前記低誘電率(low-k)誘電体層を形成する始めの段階の間に、アルゴン・プラズマによる前処理工程を行うステップと
を備えている、
請求項14に記載の方法。 - 前記酸素プラズマを、任意事項として不活性ガスと混合する、酸素ガスから生成する、
請求項19に記載の方法。 - 前記酸素プラズマによる処理工程を、6.67〜2666.4Pa(0.05〜20Torr)の動作圧力で、約5〜約60秒間行う、
請求項19に記載の方法。 - 前記酸素プラズマをRF電源を用いて生成する、
請求項19に記載の方法。 - 前記アルゴン・プラズマを、任意事項としてN、He、Xe、またはKrとともに使用する、Arガスから生成する、
請求項19に記載の方法。 - 前記アルゴン・プラズマによる前処理工程を、6.67〜2666.4Pa(0.05〜20Torr)の動作圧力で、約5〜約60秒間行う、
請求項19に記載の方法。 - 前記アルゴン・プラズマをRF電源を用いて生成する、
請求項19に記載の方法。 - 接着遷移層を形成する前記ステップが、
前記拡散障壁キャップ誘電体層の上にSiO含有層を形成するステップと、
酸素プラズマによる前処理プロセスを実行して前記接着遷移層の前記C傾斜領域を形成するステップと
を備えている、
請求項14に記載の方法。 - 前記SiO含有層を熱成長プロセスまたは堆積によって形成する、
請求項26に記載の方法。 - 前記酸素プラズマを、任意事項として不活性ガスと混合する、酸素ガスから生成する、
請求項26に記載の方法。 - 前記酸素プラズマによる前処理工程を、6.67〜2666.4Pa(0.05〜20Torr)の動作圧力で、約5〜約60秒間行う、
請求項26に記載の方法。 - 前記酸素プラズマをRF電源を用いて生成する、
請求項26に記載の方法。 - 前記上部低誘電率(low-k)誘電体層はSi、C、O、およびHから成る元素群を含んでおり、
前記拡散障壁キャップ誘電体層はC、Si、およびHから成り、任意事項としてNを含む元素群を含んでいる、
請求項14に記載の方法。 - 相互接続構造体を形成する方法であって、
C、Si、N、およびHから成る元素群を含む拡散障壁キャップ誘電体層の表面に接着遷移層を形成するステップであって、前記接着遷移層は下部SiOx (またはSiON)含有領域と上部C傾斜領域とを備えている、ステップと、
前記接着遷移層の表面に、Si、C、O、およびHから成る元素群を含む低誘電率(low-k)誘電体層を形成するステップであって、前記低誘電率(low-k)誘電体層が前記接着遷移層の前記上部C傾斜領域と接触して界面を形成している、ステップと
を備えた
方法。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010522433A (ja) * | 2007-03-23 | 2010-07-01 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 多孔SiCOH膜を含む半導体デバイス構造およびその製造方法 |
Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002001627A1 (fr) * | 2000-06-26 | 2002-01-03 | Hitachi, Ltd. | Dispositif a semi-conducteur et procede de fabrication associe |
JP4296051B2 (ja) * | 2003-07-23 | 2009-07-15 | 株式会社リコー | 半導体集積回路装置 |
US7253125B1 (en) | 2004-04-16 | 2007-08-07 | Novellus Systems, Inc. | Method to improve mechanical strength of low-k dielectric film using modulated UV exposure |
US7102232B2 (en) * | 2004-04-19 | 2006-09-05 | International Business Machines Corporation | Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer |
US9659769B1 (en) | 2004-10-22 | 2017-05-23 | Novellus Systems, Inc. | Tensile dielectric films using UV curing |
US7727880B1 (en) | 2004-11-03 | 2010-06-01 | Novellus Systems, Inc. | Protective self-aligned buffer layers for damascene interconnects |
US7727881B1 (en) | 2004-11-03 | 2010-06-01 | Novellus Systems, Inc. | Protective self-aligned buffer layers for damascene interconnects |
KR100606905B1 (ko) * | 2004-12-29 | 2006-08-01 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
US8454750B1 (en) | 2005-04-26 | 2013-06-04 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US8980769B1 (en) | 2005-04-26 | 2015-03-17 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US8889233B1 (en) | 2005-04-26 | 2014-11-18 | Novellus Systems, Inc. | Method for reducing stress in porous dielectric films |
US7846832B2 (en) * | 2005-07-07 | 2010-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
US7563704B2 (en) * | 2005-09-19 | 2009-07-21 | International Business Machines Corporation | Method of forming an interconnect including a dielectric cap having a tensile stress |
US7691736B2 (en) * | 2006-02-10 | 2010-04-06 | Infineon Technologies Ag | Minimizing low-k dielectric damage during plasma processing |
US20070238309A1 (en) * | 2006-03-31 | 2007-10-11 | Jun He | Method of reducing interconnect line to line capacitance by using a low k spacer |
EP1858071A1 (en) * | 2006-05-18 | 2007-11-21 | S.O.I.TEC. Silicon on Insulator Technologies S.A. | Method for fabricating a semiconductor on insulator type wafer and semiconductor on insulator wafer |
US7910420B1 (en) * | 2006-07-13 | 2011-03-22 | National Semiconductor Corporation | System and method for improving CMOS compatible non volatile memory retention reliability |
US7459388B2 (en) * | 2006-09-06 | 2008-12-02 | Samsung Electronics Co., Ltd. | Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses |
US8465991B2 (en) | 2006-10-30 | 2013-06-18 | Novellus Systems, Inc. | Carbon containing low-k dielectric constant recovery using UV treatment |
US10037905B2 (en) * | 2009-11-12 | 2018-07-31 | Novellus Systems, Inc. | UV and reducing treatment for K recovery and surface clean in semiconductor processing |
US7897505B2 (en) * | 2007-03-23 | 2011-03-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for enhancing adhesion between layers in BEOL fabrication |
KR100881396B1 (ko) * | 2007-06-20 | 2009-02-05 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
US8211510B1 (en) | 2007-08-31 | 2012-07-03 | Novellus Systems, Inc. | Cascaded cure approach to fabricate highly tensile silicon nitride films |
US7830010B2 (en) * | 2008-04-03 | 2010-11-09 | International Business Machines Corporation | Surface treatment for selective metal cap applications |
US20100015816A1 (en) * | 2008-07-15 | 2010-01-21 | Kelvin Chan | Methods to promote adhesion between barrier layer and porous low-k film deposited from multiple liquid precursors |
US9050623B1 (en) | 2008-09-12 | 2015-06-09 | Novellus Systems, Inc. | Progressive UV cure |
US8268722B2 (en) * | 2009-06-03 | 2012-09-18 | Novellus Systems, Inc. | Interfacial capping layers for interconnects |
JP5773306B2 (ja) * | 2010-01-15 | 2015-09-02 | ノベラス・システムズ・インコーポレーテッドNovellus Systems Incorporated | 半導体素子構造を形成する方法および装置 |
US8435901B2 (en) | 2010-06-11 | 2013-05-07 | Tokyo Electron Limited | Method of selectively etching an insulation stack for a metal interconnect |
CN102487001B (zh) * | 2010-12-01 | 2013-08-14 | 中芯国际集成电路制造(上海)有限公司 | 提高介质层的均匀性方法 |
CN102487057B (zh) * | 2010-12-03 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | 金属前介质层及其制造方法 |
US8753978B2 (en) | 2011-06-03 | 2014-06-17 | Novellus Systems, Inc. | Metal and silicon containing capping layers for interconnects |
KR101690392B1 (ko) | 2011-12-20 | 2016-12-27 | 인텔 코포레이션 | 등각 저온 밀봉 유전체 확산 장벽들 |
US10832904B2 (en) | 2012-06-12 | 2020-11-10 | Lam Research Corporation | Remote plasma based deposition of oxygen doped silicon carbide films |
US10325773B2 (en) | 2012-06-12 | 2019-06-18 | Novellus Systems, Inc. | Conformal deposition of silicon carbide films |
US9234276B2 (en) | 2013-05-31 | 2016-01-12 | Novellus Systems, Inc. | Method to obtain SiC class of films of desired composition and film properties |
US20140117511A1 (en) | 2012-10-30 | 2014-05-01 | Infineon Technologies Ag | Passivation Layer and Method of Making a Passivation Layer |
CN103021935A (zh) * | 2012-12-24 | 2013-04-03 | 上海集成电路研发中心有限公司 | 局部空气隙的形成方法 |
CN103928391A (zh) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US10297442B2 (en) * | 2013-05-31 | 2019-05-21 | Lam Research Corporation | Remote plasma based deposition of graded or multi-layered silicon carbide film |
CN105336673A (zh) * | 2014-07-28 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN105336674B (zh) * | 2014-07-28 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN105336675B (zh) * | 2014-07-29 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN105826237A (zh) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN105990217B (zh) * | 2015-01-29 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其形成方法 |
CN106158729B (zh) * | 2015-04-08 | 2019-12-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US20160314964A1 (en) | 2015-04-21 | 2016-10-27 | Lam Research Corporation | Gap fill using carbon-based films |
US9633896B1 (en) | 2015-10-09 | 2017-04-25 | Lam Research Corporation | Methods for formation of low-k aluminum-containing etch stop films |
US10326019B2 (en) | 2016-09-26 | 2019-06-18 | International Business Machines Corporation | Fully-depleted CMOS transistors with U-shaped channel |
US9847221B1 (en) | 2016-09-29 | 2017-12-19 | Lam Research Corporation | Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing |
US10002787B2 (en) | 2016-11-23 | 2018-06-19 | Lam Research Corporation | Staircase encapsulation in 3D NAND fabrication |
US20190157213A1 (en) | 2017-11-20 | 2019-05-23 | Globalfoundries Inc. | Semiconductor structure with substantially straight contact profile |
US10840087B2 (en) | 2018-07-20 | 2020-11-17 | Lam Research Corporation | Remote plasma based deposition of boron nitride, boron carbide, and boron carbonitride films |
KR102668080B1 (ko) | 2018-07-24 | 2024-05-22 | 삼성전자주식회사 | 반도체 소자 |
CN109585264B (zh) * | 2018-08-26 | 2020-12-22 | 合肥安德科铭半导体科技有限公司 | 一种氮化硅薄膜的可流动化学气相沉积方法 |
KR20230085954A (ko) | 2018-10-19 | 2023-06-14 | 램 리써치 코포레이션 | 갭 충진 (gapfill) 을 위한 도핑되거나 도핑되지 않은 실리콘 카바이드 증착 및 원격 수소 플라즈마 노출 |
CN111044183B (zh) * | 2019-12-24 | 2022-03-18 | 浙江清华柔性电子技术研究院 | 柔性压力传感及其制备方法 |
US11791155B2 (en) * | 2020-08-27 | 2023-10-17 | Applied Materials, Inc. | Diffusion barriers for germanium |
US20240071817A1 (en) * | 2022-08-26 | 2024-02-29 | Applied Materials, Inc. | Adhesion improvement between low-k materials and cap layers |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1041119C (zh) * | 1994-04-01 | 1998-12-09 | 吉林大学 | 含金刚石膜的soi集成电路芯片材料及其制作工艺 |
US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US6303192B1 (en) * | 1998-07-22 | 2001-10-16 | Philips Semiconductor Inc. | Process to improve adhesion of PECVD cap layers in integrated circuits |
US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
US6593653B2 (en) * | 1999-09-30 | 2003-07-15 | Novellus Systems, Inc. | Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications |
US6465365B1 (en) * | 2000-04-07 | 2002-10-15 | Koninklijke Philips Electronics N.V. | Method of improving adhesion of cap oxide to nanoporous silica for integrated circuit fabrication |
US20030008493A1 (en) * | 2001-07-03 | 2003-01-09 | Shyh-Dar Lee | Interconnect structure manufacturing |
US6570256B2 (en) * | 2001-07-20 | 2003-05-27 | International Business Machines Corporation | Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates |
US6737747B2 (en) | 2002-01-15 | 2004-05-18 | International Business Machines Corporation | Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof |
US6649512B1 (en) * | 2002-06-07 | 2003-11-18 | Silicon Integrated Systems Corp. | Method for improving adhesion of a low k dielectric to a barrier layer |
US6525428B1 (en) * | 2002-06-28 | 2003-02-25 | Advance Micro Devices, Inc. | Graded low-k middle-etch stop layer for dual-inlaid patterning |
US20040018697A1 (en) * | 2002-07-26 | 2004-01-29 | Chung Henry Wei-Ming | Method and structure of interconnection with anti-reflection coating |
US6974762B2 (en) * | 2002-08-01 | 2005-12-13 | Intel Corporation | Adhesion of carbon doped oxides by silanization |
US6756321B2 (en) | 2002-10-05 | 2004-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant |
US6974768B1 (en) * | 2003-01-15 | 2005-12-13 | Novellus Systems, Inc. | Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films |
US7067437B2 (en) | 2003-09-12 | 2006-06-27 | International Business Machines Corporation | Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same |
US7144828B2 (en) * | 2004-01-30 | 2006-12-05 | Chartered Semiconductor Manufacturing Ltd. | He treatment to improve low-k adhesion property |
US7102232B2 (en) * | 2004-04-19 | 2006-09-05 | International Business Machines Corporation | Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer |
-
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010522433A (ja) * | 2007-03-23 | 2010-07-01 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 多孔SiCOH膜を含む半導体デバイス構造およびその製造方法 |
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US20070148958A1 (en) | 2007-06-28 |
JP4288251B2 (ja) | 2009-07-01 |
TWI334641B (en) | 2010-12-11 |
US20080254643A1 (en) | 2008-10-16 |
US7102232B2 (en) | 2006-09-05 |
CN1691323A (zh) | 2005-11-02 |
US20050230831A1 (en) | 2005-10-20 |
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