JP2004363558A - 半導体装置の製造方法およびプラズマエッチング装置のクリーニング方法 - Google Patents
半導体装置の製造方法およびプラズマエッチング装置のクリーニング方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
【解決手段】 半導体基板1上に低誘電率絶縁膜5を形成する工程と、低誘電率絶縁膜上にレジストパターン6を形成する工程と、レジストパターンをマスクとして低誘電率絶縁膜をエッチングする工程と、アンモニウムイオンによるプラズマ処理によってレジストパターン6を剥離する工程と、を備えている。
【選択図】 図2
Description
O≡Si−CH3 + 2H → O≡Si−H + CH4
また、メチルシロキサンとN2とは以下の反応が起こる。
O≡Si−CH3 + N → O≡Si−C−NH2 または O≡Si−NH2 + HCN
すなわち、メチルシロキサンはH2との反応でSi−CH3結合を消失し、Si−H結合を生成するため吸湿性を持ってしまい、容易にSi−O結合へと膜が変質するという問題が発生する。
図1(a)乃至図2(c)は本発明の第1実施形態に係る半導体装置の製造工程を示した断面図である。
NH3 → NH2 + + H* , NH2 → NH+ + H*
ここで、「H*」は水素ラジカルを表す。このNH2 +イオン又はNH+イオンがレジストと
C+NH2 +(又はNH+)→H2CN(又はHCN)
の反応をすることによってレジストを剥離している。
O≡Si−CH3+NH2 +(又はNH+)→O≡Si−CH2−NH2(又はO≡Si−NH2)
このようにNH3ガスを用いると、表出しているメチルシロキサン膜5はアンモニウムイオン(NH2 +又はNH+)と反応し、Si−N結合又はC−N結合を有する保護膜7となって、メチルシロキサン膜5を保護することができる(図2(b)参照)。
次に、本発明の第2実施形態による半導体装置の製造方法を、図7を参照して説明する。
次に、第1および第2実施形態の製造方法で用いるプラズマエッチング装置において問題となるレジストの剥離速度の低下について説明する。ウェハの処理枚数の増加と共にプラズマエッチング処理を行う処理容器内にはレジストとの反応生成物やウェハから持ち込まれた配線材料のCu等の金属不純物が蓄積される。このような堆積物にエッチャントが消費されレジストの剥離速度が低下するという問題があった。
5 第2の層間絶縁膜(メチルシロキサン膜)
6 レジストパターン
Claims (5)
- 半導体基板上に低誘電率絶縁膜を形成する工程と、
前記低誘電率絶縁膜上にレジストパターンを形成する工程と、
前記レジストパターンをマスクとして前記低誘電率絶縁膜をエッチングする工程と、
アンモニウムイオンによるプラズマ処理によって前記レジストパターンを剥離する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 半導体基板上に低誘電率絶縁膜を形成する工程と、
前記低誘電率絶縁膜上にレジストパターンを形成する工程と、
前記レジストパターンをマスクとして前記低誘電率絶縁膜をエッチングする工程と、
NH3、HCNからなる群から選ばれた窒素化合物ガスをプラズマにより励起した窒素活性種による、プラズマの電子密度が1×1011cm−3以下となるプラズマ処理によって前記レジストパターンを剥離する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記レジストパターンを剥離する工程は、
He、Ne、Ar、Kr、Xe、Rnよりなる群から選ばれた不活性ガスをプラズマ処理中に添加することを特徴とする請求項1または2記載の半導体装置の製造方法。 - 前記低誘電率絶縁膜内に複数の配線を形成する工程をさらに備え、
前記低誘電率絶縁膜は空孔を有し、この空孔の直径は前記配線の配線間隔の5%以下であることを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。 - 基板表面に形成されたレジストを真空容器内でプラズマエッチングにより剥離するプラズマエッチング装置のクリーニング方法であって、
NH3ガスを前記真空容器内に供給する工程と、
前記真空容器内でプラズマを生成させ、前記真空容器内に付着した堆積物を除去する工程と、
を備えたことを特徴とするプラズマエッチング装置のクリーニング方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004105896A JP2004363558A (ja) | 2003-05-13 | 2004-03-31 | 半導体装置の製造方法およびプラズマエッチング装置のクリーニング方法 |
TW093111908A TW200425251A (en) | 2003-05-13 | 2004-04-28 | Method for producing semiconductor device and method for cleaning plasma etching device |
CNA2004100381565A CN1551307A (zh) | 2003-05-13 | 2004-05-11 | 半导体器件的制造方法和等离子体蚀刻装置的清洁方法 |
US10/843,508 US20050009356A1 (en) | 2003-05-13 | 2004-05-12 | Method of manufacturing semiconductor device and method of cleaning plasma etching apparatus used therefor |
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JP2003134714 | 2003-05-13 | ||
JP2004105896A JP2004363558A (ja) | 2003-05-13 | 2004-03-31 | 半導体装置の製造方法およびプラズマエッチング装置のクリーニング方法 |
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JP2004363558A true JP2004363558A (ja) | 2004-12-24 |
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JP2004105896A Pending JP2004363558A (ja) | 2003-05-13 | 2004-03-31 | 半導体装置の製造方法およびプラズマエッチング装置のクリーニング方法 |
Country Status (4)
Country | Link |
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US (1) | US20050009356A1 (ja) |
JP (1) | JP2004363558A (ja) |
CN (1) | CN1551307A (ja) |
TW (1) | TW200425251A (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008545253A (ja) * | 2005-05-10 | 2008-12-11 | ラム リサーチ コーポレーション | 通常の低k誘電性材料および/または多孔質の低k誘電性材料の存在下でのレジスト剥離のための方法 |
JP2009105272A (ja) * | 2007-10-24 | 2009-05-14 | Tokyo Electron Ltd | プラズマエッチング方法及び記憶媒体 |
JP2012023245A (ja) * | 2010-07-15 | 2012-02-02 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
JP2015529014A (ja) * | 2012-07-16 | 2015-10-01 | マットソン テクノロジー インコーポレイテッドMattson Technology, Inc. | 純還元性プラズマ中で高アスペクト比のフォトレジストを除去する方法 |
CN106252274A (zh) * | 2015-06-11 | 2016-12-21 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
Families Citing this family (9)
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US7253116B2 (en) * | 2004-11-18 | 2007-08-07 | International Business Machines Corporation | High ion energy and reative species partial pressure plasma ash process |
US7393795B2 (en) * | 2006-02-01 | 2008-07-01 | Applied Materials, Inc. | Methods for post-etch deposition of a dielectric film |
JP4675258B2 (ja) * | 2006-02-22 | 2011-04-20 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法および半導体装置 |
JP2008053507A (ja) * | 2006-08-25 | 2008-03-06 | Matsushita Electric Ind Co Ltd | ドライエッチング方法 |
US20090078675A1 (en) * | 2007-09-26 | 2009-03-26 | Silverbrook Research Pty Ltd | Method of removing photoresist |
WO2009039551A1 (en) * | 2007-09-26 | 2009-04-02 | Silverbrook Research Pty Ltd | Method of removing photoresist |
JP2009188257A (ja) * | 2008-02-07 | 2009-08-20 | Tokyo Electron Ltd | プラズマエッチング方法及びプラズマエッチング装置並びに記憶媒体 |
US8030957B2 (en) | 2009-03-25 | 2011-10-04 | Aehr Test Systems | System for testing an integrated circuit of a device and its method of use |
JP2016178222A (ja) * | 2015-03-20 | 2016-10-06 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6277733B1 (en) * | 1998-10-05 | 2001-08-21 | Texas Instruments Incorporated | Oxygen-free, dry plasma process for polymer removal |
US6316354B1 (en) * | 1999-10-26 | 2001-11-13 | Lsi Logic Corporation | Process for removing resist mask of integrated circuit structure which mitigates damage to underlying low dielectric constant silicon oxide dielectric layer |
US6440864B1 (en) * | 2000-06-30 | 2002-08-27 | Applied Materials Inc. | Substrate cleaning process |
US6455431B1 (en) * | 2000-08-01 | 2002-09-24 | Applied Materials Inc. | NH3 plasma descumming and resist stripping in semiconductor applications |
JP2002261092A (ja) * | 2001-02-27 | 2002-09-13 | Nec Corp | 半導体装置の製造方法 |
-
2004
- 2004-03-31 JP JP2004105896A patent/JP2004363558A/ja active Pending
- 2004-04-28 TW TW093111908A patent/TW200425251A/zh unknown
- 2004-05-11 CN CNA2004100381565A patent/CN1551307A/zh active Pending
- 2004-05-12 US US10/843,508 patent/US20050009356A1/en not_active Abandoned
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008545253A (ja) * | 2005-05-10 | 2008-12-11 | ラム リサーチ コーポレーション | 通常の低k誘電性材料および/または多孔質の低k誘電性材料の存在下でのレジスト剥離のための方法 |
JP2014090192A (ja) * | 2005-05-10 | 2014-05-15 | Lam Research Corporation | 通常の低k誘電性材料および/または多孔質の低k誘電性材料の存在下でのレジスト剥離のための方法 |
JP2009105272A (ja) * | 2007-10-24 | 2009-05-14 | Tokyo Electron Ltd | プラズマエッチング方法及び記憶媒体 |
JP2012023245A (ja) * | 2010-07-15 | 2012-02-02 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
US9337093B2 (en) | 2010-07-15 | 2016-05-10 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
JP2015529014A (ja) * | 2012-07-16 | 2015-10-01 | マットソン テクノロジー インコーポレイテッドMattson Technology, Inc. | 純還元性プラズマ中で高アスペクト比のフォトレジストを除去する方法 |
CN106252274A (zh) * | 2015-06-11 | 2016-12-21 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
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Publication number | Publication date |
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TW200425251A (en) | 2004-11-16 |
CN1551307A (zh) | 2004-12-01 |
US20050009356A1 (en) | 2005-01-13 |
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