JP2009105272A - プラズマエッチング方法及び記憶媒体 - Google Patents
プラズマエッチング方法及び記憶媒体 Download PDFInfo
- Publication number
- JP2009105272A JP2009105272A JP2007276500A JP2007276500A JP2009105272A JP 2009105272 A JP2009105272 A JP 2009105272A JP 2007276500 A JP2007276500 A JP 2007276500A JP 2007276500 A JP2007276500 A JP 2007276500A JP 2009105272 A JP2009105272 A JP 2009105272A
- Authority
- JP
- Japan
- Prior art keywords
- gas
- etching method
- plasma
- insulating film
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 75
- 238000001020 plasma etching Methods 0.000 title claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 89
- 238000005530 etching Methods 0.000 claims abstract description 65
- 239000011229 interlayer Substances 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000010949 copper Substances 0.000 claims abstract description 32
- 229910052802 copper Inorganic materials 0.000 claims abstract description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 abstract description 31
- 230000008021 deposition Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 155
- 235000012431 wafers Nutrition 0.000 description 31
- 239000007795 chemical reaction product Substances 0.000 description 22
- 230000006870 function Effects 0.000 description 15
- 238000006243 chemical reaction Methods 0.000 description 11
- 238000000354 decomposition reaction Methods 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 239000003507 refrigerant Substances 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 150000002222 fluorine compounds Chemical class 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical group [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Analytical Chemistry (AREA)
- Plasma & Fusion (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】ウエハWに形成されたCwFx(x、wは所定の自然数)からなる低誘電率層間絶縁膜41と、エッチングストップ層42と、銅配線43と、メタルハードマスク45とを有する半導体デバイス40に施されるエッチングストップ層除去処理において、低誘電率層間絶縁膜41と銅配線43及び/又はメタルハードマスク45とが、CF4ガス及びN2ガスを含む処理ガスから生じたプラズマへ同時に晒される際、当該処理ガスにおけるCF4ガス及びN2ガスの流量比はCF4ガス:N2ガス=1:X(但し、X≧7)で示される。
【選択図】図4
Description
(1)トレンチ46の底部における低誘電率層間絶縁膜41のエッチングにおいて、CwFxが分解されてCが大量に飛散する。一方、ビアホール47の底部に露出した銅配線43がスパッタされてCuが飛散し、さらに、メタルハードマスク45がスパッタされてTiも飛散する。
(2)大量に飛散したCと、Cu又はTiとが結合して反応生成物が大量に生成され、ビアホール47やトレンチ46の底部や側面に残渣48として付着する。
(3)一方、多孔性SiO2膜等では、低誘電率層間絶縁膜がエッチングされてもCが大量に飛散することがなく、せいぜいSiに起因する反応生成物が発生するのみである。また、Siに起因する反応生成物はFのプラズマによってSiO2膜とほぼ同じエッチレート(SiO2膜に対するSiに起因する反応生成物の選択比はほぼ1である)でエッチングされるが、CF4ガスからは大量にFのプラズマが発生するので、Siに起因する反応生成物は殆ど除去され、その結果、ビアホールやトレンチの底部や側面に残渣が付着しない。
まず、本発明者は、半導体デバイス40が形成されたウエハWを準備し、基板処理装置10によって半導体デバイス40に図4のエッチングストップ層除去処理を施した。その後、トレンチ46やビアホール47の底部及び側面を観察したところ、残渣48が付着していないことを確認した。
次に、本発明者は、実施例と同様に、半導体デバイス40が形成されたウエハWを準備し、基板処理装置10によって半導体デバイス40にエッチングストップ層除去処理を施した。このときに施されたエッチングストップ層除去処理の条件は、処理ガスとしてCF4ガス及びN2ガスの流量が等しい混合ガスを用いた以外、図4の処理の条件と同じであった。その後、トレンチ46やビアホール47の底部及び側面を観察したところ、残渣48が付着していることを確認した。
40,50 半導体デバイス
41,51 低誘電率層間絶縁膜
42 エッチングストップ層
43 銅配線
45,52 メタルハードマスク
46,53 トレンチ
47 ビアホール
48 残渣
Claims (6)
- 基板に形成されたCwFx(x、wは所定の自然数)からなる層間絶縁膜と金属層又は金属含有層とが処理ガスから生じたプラズマへ同時に晒されるプラズマエッチング方法であって、
前記処理ガスはCyFz(y、zは所定の自然数)ガス及びN2ガスを含む混合ガスであり、
前記処理ガスにおける前記N2ガスの流量は前記CyFzガスの流量よりも大きいことを特徴とするプラズマエッチング方法。 - 前記処理ガスにおける前記CyFzガス及び前記N2ガスの流量比は下記式(1)
CyFzガス:N2ガス = 1:X、但し、X≧7 … (1)
で示されることを特徴とする請求項1記載のプラズマエッチング方法。 - 前記金属層は銅からなり、該金属層は前記層間絶縁膜の下に形成されたエッチングストップ層によって覆われることを特徴とする請求項1又は2記載のプラズマエッチング方法。
- 前記エッチングストップ層はSiC層又はSiCN層であることを特徴とする請求項3記載のプラズマエッチング方法。
- 前記金属含有層は前記層間絶縁膜の上に所定のパターンで形成されるハードマスクであることを特徴とする請求項1又は2記載のプラズマエッチング方法。
- 基板に形成されたCwFx(x、wは所定の自然数)からなる層間絶縁膜と金属層又は金属含有層とが処理ガスから生じたプラズマへ同時に晒されるプラズマエッチング方法をコンピュータに実行させるプログラムを格納するコンピュータで読み取り可能な記憶媒体であって、
前記処理ガスはCyFz(y、zは所定の自然数)ガス及びN2ガスを含む混合ガスであり、
前記処理ガスにおける前記N2ガスの流量は前記CyFzガスの流量よりも大きいことを特徴とする記憶媒体。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007276500A JP5072531B2 (ja) | 2007-10-24 | 2007-10-24 | プラズマエッチング方法及び記憶媒体 |
US12/254,943 US9384999B2 (en) | 2007-10-24 | 2008-10-21 | Plasma etching method and storage medium |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007276500A JP5072531B2 (ja) | 2007-10-24 | 2007-10-24 | プラズマエッチング方法及び記憶媒体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009105272A true JP2009105272A (ja) | 2009-05-14 |
JP5072531B2 JP5072531B2 (ja) | 2012-11-14 |
Family
ID=40583388
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007276500A Expired - Fee Related JP5072531B2 (ja) | 2007-10-24 | 2007-10-24 | プラズマエッチング方法及び記憶媒体 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9384999B2 (ja) |
JP (1) | JP5072531B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8759212B2 (en) | 2010-05-07 | 2014-06-24 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing semiconductor device |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120083129A1 (en) * | 2010-10-05 | 2012-04-05 | Skyworks Solutions, Inc. | Apparatus and methods for focusing plasma |
US9478428B2 (en) | 2010-10-05 | 2016-10-25 | Skyworks Solutions, Inc. | Apparatus and methods for shielding a plasma etcher electrode |
GB201217712D0 (en) * | 2012-10-03 | 2012-11-14 | Spts Technologies Ltd | methods of plasma etching |
US20230395385A1 (en) * | 2022-06-06 | 2023-12-07 | Tokyo Electron Limited | Plasma etching tools and systems |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000183040A (ja) * | 1998-12-15 | 2000-06-30 | Canon Inc | 有機層間絶縁膜エッチング後のレジストアッシング方法 |
JP2000216135A (ja) * | 1999-01-27 | 2000-08-04 | Matsushita Electric Ind Co Ltd | エッチング方法 |
JP2004363558A (ja) * | 2003-05-13 | 2004-12-24 | Toshiba Corp | 半導体装置の製造方法およびプラズマエッチング装置のクリーニング方法 |
JP2005005697A (ja) * | 2003-05-21 | 2005-01-06 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
JP2005033168A (ja) * | 2003-07-10 | 2005-02-03 | Samsung Electronics Co Ltd | 半導体素子の金属配線の形成方法 |
JP2006270019A (ja) * | 2004-06-21 | 2006-10-05 | Tokyo Electron Ltd | プラズマ処理装置およびプラズマ処理方法、ならびにコンピュータ読み取り可能な記憶媒体 |
JP2007049069A (ja) * | 2005-08-12 | 2007-02-22 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5849639A (en) * | 1997-11-26 | 1998-12-15 | Lucent Technologies Inc. | Method for removing etching residues and contaminants |
JP2002110644A (ja) | 2000-09-28 | 2002-04-12 | Nec Corp | エッチング方法 |
US20040209468A1 (en) * | 2003-04-17 | 2004-10-21 | Applied Materials Inc. | Method for fabricating a gate structure of a field effect transistor |
US7125792B2 (en) * | 2003-10-14 | 2006-10-24 | Infineon Technologies Ag | Dual damascene structure and method |
JP4492947B2 (ja) * | 2004-07-23 | 2010-06-30 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
WO2009047588A1 (en) * | 2007-10-09 | 2009-04-16 | Freescale Semiconductor, Inc. | Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method |
-
2007
- 2007-10-24 JP JP2007276500A patent/JP5072531B2/ja not_active Expired - Fee Related
-
2008
- 2008-10-21 US US12/254,943 patent/US9384999B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000183040A (ja) * | 1998-12-15 | 2000-06-30 | Canon Inc | 有機層間絶縁膜エッチング後のレジストアッシング方法 |
JP2000216135A (ja) * | 1999-01-27 | 2000-08-04 | Matsushita Electric Ind Co Ltd | エッチング方法 |
JP2004363558A (ja) * | 2003-05-13 | 2004-12-24 | Toshiba Corp | 半導体装置の製造方法およびプラズマエッチング装置のクリーニング方法 |
JP2005005697A (ja) * | 2003-05-21 | 2005-01-06 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
JP2005033168A (ja) * | 2003-07-10 | 2005-02-03 | Samsung Electronics Co Ltd | 半導体素子の金属配線の形成方法 |
JP2006270019A (ja) * | 2004-06-21 | 2006-10-05 | Tokyo Electron Ltd | プラズマ処理装置およびプラズマ処理方法、ならびにコンピュータ読み取り可能な記憶媒体 |
JP2007049069A (ja) * | 2005-08-12 | 2007-02-22 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8759212B2 (en) | 2010-05-07 | 2014-06-24 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US9384999B2 (en) | 2016-07-05 |
JP5072531B2 (ja) | 2012-11-14 |
US20090111275A1 (en) | 2009-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2469582B1 (en) | Substrate processing method | |
US7662723B2 (en) | Methods and apparatus for in-situ substrate processing | |
JP4963842B2 (ja) | 基板処理室の洗浄方法、記憶媒体及び基板処理装置 | |
JP5701654B2 (ja) | 基板処理方法 | |
JP5982223B2 (ja) | プラズマ処理方法、及びプラズマ処理装置 | |
JP2010206051A (ja) | 基板処理方法 | |
JP2008198659A (ja) | プラズマエッチング方法 | |
US9130018B2 (en) | Plasma etching method and storage medium | |
JP2007242870A (ja) | 基板処理装置、基板吸着方法及び記憶媒体 | |
JP2010192668A (ja) | プラズマ処理方法 | |
JP5072531B2 (ja) | プラズマエッチング方法及び記憶媒体 | |
TWI684201B (zh) | 被處理體之處理方法 | |
JP5698558B2 (ja) | 基板処理方法及び記憶媒体 | |
US8870164B2 (en) | Substrate processing method and storage medium | |
TWI694481B (zh) | 處理被處理體之方法 | |
JP2006156486A (ja) | 基板処理方法および半導体装置の製造方法 | |
JP4827567B2 (ja) | プラズマエッチング方法およびコンピュータ読み取り可能な記憶媒体 | |
JP2010003807A (ja) | 半導体装置の製造方法 | |
JP5011782B2 (ja) | 半導体装置の製造方法、プラズマ処理装置及び記憶媒体。 | |
KR101828082B1 (ko) | 표면 평탄화 방법 | |
JP2007250861A (ja) | プラズマエッチング方法、プラズマエッチング装置及びコンピュータ記憶媒体 | |
JP2007059666A (ja) | 半導体装置の製造方法、半導体装置の製造装置、制御プログラム及びコンピュータ記憶媒体 | |
JP2006196663A (ja) | エッチング方法,プログラム,コンピュータ読み取り可能な記録媒体及びプラズマ処理装置 | |
KR20190015132A (ko) | 피처리체를 처리하는 방법 | |
JP2017224797A (ja) | 銅層をエッチングする方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100917 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120315 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120321 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120517 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120724 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120821 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150831 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |