HK1198783A1 - Method of manufacturing semiconductor device and semiconductor device - Google Patents
Method of manufacturing semiconductor device and semiconductor device Download PDFInfo
- Publication number
- HK1198783A1 HK1198783A1 HK14112255.9A HK14112255A HK1198783A1 HK 1198783 A1 HK1198783 A1 HK 1198783A1 HK 14112255 A HK14112255 A HK 14112255A HK 1198783 A1 HK1198783 A1 HK 1198783A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- semiconductor chip
- chip
- semiconductor
- wire
- die pad
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/811—Multiple chips on leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/411—Chip-supporting parts, e.g. die pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
- H10W70/424—Cross-sectional shapes
- H10W70/427—Bent parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/456—Materials
- H10W70/457—Materials of metallic layers on leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/27—Structural arrangements therefor
- H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
- H10W46/503—Located in scribe lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/461—Leadframes specially adapted for cooling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07532—Compression bonding, e.g. thermocompression bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07532—Compression bonding, e.g. thermocompression bonding
- H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013-099833 | 2013-05-10 | ||
| JP2013099833A JP2014220439A (ja) | 2013-05-10 | 2013-05-10 | 半導体装置の製造方法および半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| HK1198783A1 true HK1198783A1 (en) | 2015-06-05 |
Family
ID=51852663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| HK14112255.9A HK1198783A1 (en) | 2013-05-10 | 2014-12-04 | Method of manufacturing semiconductor device and semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US9275945B2 (https=) |
| JP (1) | JP2014220439A (https=) |
| CN (1) | CN104143518A (https=) |
| HK (1) | HK1198783A1 (https=) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9893058B2 (en) * | 2015-09-17 | 2018-02-13 | Semiconductor Components Industries, Llc | Method of manufacturing a semiconductor device having reduced on-state resistance and structure |
| JP6673012B2 (ja) * | 2016-05-26 | 2020-03-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| DE102017202770B4 (de) * | 2016-08-31 | 2023-06-07 | Infineon Technologies Austria Ag | Halbleiterchipgehäuse mit einem sich wiederholenden Grundflächenmuster |
| JP2018107416A (ja) * | 2016-12-28 | 2018-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP2018137342A (ja) * | 2017-02-22 | 2018-08-30 | 株式会社村田製作所 | 半導体装置及びその製造方法 |
| US10741466B2 (en) | 2017-11-17 | 2020-08-11 | Infineon Technologies Ag | Formation of conductive connection tracks in package mold body using electroless plating |
| US10777536B2 (en) | 2017-12-08 | 2020-09-15 | Infineon Technologies Ag | Semiconductor package with air cavity |
| JP7199167B2 (ja) | 2018-06-29 | 2023-01-05 | 三菱電機株式会社 | パワー半導体モジュール、電力変換装置、およびパワー半導体モジュールの製造方法 |
| US10796981B1 (en) | 2019-04-04 | 2020-10-06 | Infineon Technologies Ag | Chip to lead interconnect in encapsulant of molded semiconductor package |
| US11133281B2 (en) | 2019-04-04 | 2021-09-28 | Infineon Technologies Ag | Chip to chip interconnect in encapsulant of molded semiconductor package |
| CN112018052A (zh) | 2019-05-31 | 2020-12-01 | 英飞凌科技奥地利有限公司 | 具有可激光活化模制化合物的半导体封装 |
| KR102119142B1 (ko) * | 2019-10-01 | 2020-06-05 | 해성디에스 주식회사 | 웨이퍼 레벨 패키지의 캐리어를 리드 프레임으로 제작하는 방법 |
| CN111354718B (zh) * | 2020-03-23 | 2022-02-25 | 江苏中科智芯集成科技有限公司 | 含多芯片封装结构的芯片排列布线方法、装置及电子设备 |
| US11587800B2 (en) | 2020-05-22 | 2023-02-21 | Infineon Technologies Ag | Semiconductor package with lead tip inspection feature |
| DE102021104696A1 (de) * | 2021-02-26 | 2022-09-01 | Infineon Technologies Ag | Verfahren zur verbindung eines elektrischen bauelementes mit einer bodeneinheit unter verwendung einer lötfreien verbindung |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10335366A (ja) * | 1997-05-30 | 1998-12-18 | Sanyo Electric Co Ltd | 半導体装置 |
| JP3039488B2 (ja) * | 1997-11-21 | 2000-05-08 | 日本電気株式会社 | 半導体装置 |
| JP3768761B2 (ja) * | 2000-01-31 | 2006-04-19 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
| JP2002076234A (ja) * | 2000-08-23 | 2002-03-15 | Rohm Co Ltd | 樹脂封止型半導体装置 |
| US20020180020A1 (en) * | 2001-06-01 | 2002-12-05 | Chih-Wen Lin | Three-dimension multi-chip stack package technology |
| JP4605996B2 (ja) * | 2003-05-29 | 2011-01-05 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
| JP4489485B2 (ja) * | 2004-03-31 | 2010-06-23 | 株式会社ルネサステクノロジ | 半導体装置 |
| JP4357344B2 (ja) * | 2004-04-16 | 2009-11-04 | 株式会社ルネサステクノロジ | 半導体装置 |
| KR100630741B1 (ko) * | 2005-03-04 | 2006-10-02 | 삼성전자주식회사 | 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법 |
| JP4881620B2 (ja) * | 2006-01-06 | 2012-02-22 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| JP4900661B2 (ja) * | 2006-02-22 | 2012-03-21 | ルネサスエレクトロニクス株式会社 | 不揮発性記憶装置 |
| US7969022B1 (en) * | 2007-03-21 | 2011-06-28 | Marvell International Ltd. | Die-to-die wire-bonding |
| JP5239309B2 (ja) * | 2007-11-21 | 2013-07-17 | 株式会社村田製作所 | 半導体装置 |
| JP5183186B2 (ja) * | 2007-12-14 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2010087129A (ja) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
| JP2010165777A (ja) * | 2009-01-14 | 2010-07-29 | Renesas Technology Corp | 半導体装置及びその製造方法 |
| KR101601847B1 (ko) * | 2009-05-21 | 2016-03-09 | 삼성전자주식회사 | 반도체 패키지 |
| JP5237900B2 (ja) * | 2009-08-11 | 2013-07-17 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP5302175B2 (ja) | 2009-12-14 | 2013-10-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP5689462B2 (ja) * | 2010-05-12 | 2015-03-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| CN102184907A (zh) * | 2011-04-19 | 2011-09-14 | 无锡红光微电子有限公司 | To3p防水密封引线框架 |
| JP5266371B2 (ja) * | 2011-08-04 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| JP6129659B2 (ja) * | 2013-06-25 | 2017-05-17 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
-
2013
- 2013-05-10 JP JP2013099833A patent/JP2014220439A/ja active Pending
-
2014
- 2014-04-23 US US14/259,842 patent/US9275945B2/en active Active
- 2014-05-12 CN CN201410199214.6A patent/CN104143518A/zh active Pending
- 2014-12-04 HK HK14112255.9A patent/HK1198783A1/xx unknown
-
2016
- 2016-02-04 US US15/015,607 patent/US9385072B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20160155710A1 (en) | 2016-06-02 |
| US9385072B2 (en) | 2016-07-05 |
| US9275945B2 (en) | 2016-03-01 |
| JP2014220439A (ja) | 2014-11-20 |
| US20140332942A1 (en) | 2014-11-13 |
| CN104143518A (zh) | 2014-11-12 |
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