HK1010465A1 - Hidden self-refresh method and apparatus for synchronous dynamic random access memory - Google Patents

Hidden self-refresh method and apparatus for synchronous dynamic random access memory

Info

Publication number
HK1010465A1
HK1010465A1 HK98111121A HK98111121A HK1010465A1 HK 1010465 A1 HK1010465 A1 HK 1010465A1 HK 98111121 A HK98111121 A HK 98111121A HK 98111121 A HK98111121 A HK 98111121A HK 1010465 A1 HK1010465 A1 HK 1010465A1
Authority
HK
Hong Kong
Prior art keywords
random access
access memory
dynamic random
synchronous dynamic
refresh method
Prior art date
Application number
HK98111121A
Other languages
English (en)
Inventor
Ho Jung Chang
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Publication of HK1010465A1 publication Critical patent/HK1010465A1/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
HK98111121A 1993-11-08 1998-10-07 Hidden self-refresh method and apparatus for synchronous dynamic random access memory HK1010465A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930023636A KR950014089B1 (ko) 1993-11-08 1993-11-08 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치

Publications (1)

Publication Number Publication Date
HK1010465A1 true HK1010465A1 (en) 1999-06-17

Family

ID=19367576

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98111121A HK1010465A1 (en) 1993-11-08 1998-10-07 Hidden self-refresh method and apparatus for synchronous dynamic random access memory

Country Status (6)

Country Link
US (1) US5511033A (xx)
JP (1) JP2781350B2 (xx)
KR (1) KR950014089B1 (xx)
DE (1) DE4439817C2 (xx)
GB (1) GB2284692B (xx)
HK (1) HK1010465A1 (xx)

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US6028804A (en) * 1998-03-09 2000-02-22 Monolithic System Technology, Inc. Method and apparatus for 1-T SRAM compatible memory
US6504780B2 (en) * 1998-10-01 2003-01-07 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a dram device using clock division
US6898140B2 (en) 1998-10-01 2005-05-24 Monolithic System Technology, Inc. Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
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US6707743B2 (en) 1998-10-01 2004-03-16 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
US6415353B1 (en) 1998-10-01 2002-07-02 Monolithic System Technology, Inc. Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
KR100351889B1 (ko) * 1998-11-13 2002-11-18 주식회사 하이닉스반도체 카스(cas)레이턴시(latency) 제어 회로
JP2000163956A (ja) * 1998-11-24 2000-06-16 Sharp Corp 半導体記憶装置
KR100557975B1 (ko) * 1998-12-31 2006-05-17 주식회사 하이닉스반도체 메모리의 자동 리프레쉬 회로_
US6282606B1 (en) * 1999-04-02 2001-08-28 Silicon Aquarius, Inc. Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods
US6327209B1 (en) 2000-08-30 2001-12-04 Micron Technology, Inc. Multi stage refresh control of a memory device
JP2002157880A (ja) * 2000-11-15 2002-05-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR100472723B1 (ko) * 2000-12-26 2005-03-08 주식회사 하이닉스반도체 뱅크 리프레쉬 제어 장치 및 방법
JP2004288226A (ja) * 2001-03-30 2004-10-14 Internatl Business Mach Corp <Ibm> Ｄｒａｍ及びｄｒａｍのリフレッシュ方法
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
US6590822B2 (en) * 2001-05-07 2003-07-08 Samsung Electronics Co., Ltd. System and method for performing partial array self-refresh operation in a semiconductor memory device
JP2002352598A (ja) * 2001-05-28 2002-12-06 Mitsubishi Electric Corp 半導体記憶装置
JP4743999B2 (ja) * 2001-05-28 2011-08-10 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100429872B1 (ko) * 2001-06-27 2004-05-04 삼성전자주식회사 반도체 메모리 장치의 이용 효율을 높이는 메모리 시스템및 상기 반도체 메모리 장치의 리프레쉬 방법
GB2380035B (en) 2001-09-19 2003-08-20 3Com Corp DRAM refresh command operation
US6671218B2 (en) 2001-12-11 2003-12-30 International Business Machines Corporation System and method for hiding refresh cycles in a dynamic type content addressable memory
US7043599B1 (en) * 2002-06-20 2006-05-09 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
US6795364B1 (en) * 2003-02-28 2004-09-21 Monolithic System Technology, Inc. Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode
JP2005222581A (ja) 2004-02-03 2005-08-18 Renesas Technology Corp 半導体記憶装置
JP4664622B2 (ja) * 2004-05-20 2011-04-06 株式会社東芝 半導体集積回路装置
US7274618B2 (en) * 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
JP4894306B2 (ja) * 2006-03-09 2012-03-14 富士通セミコンダクター株式会社 半導体メモリ、メモリシステムおよび半導体メモリの動作方法
JP5446384B2 (ja) * 2009-03-30 2014-03-19 富士通セミコンダクター株式会社 インターフェース回路、メモリシステム、およびアクセス制御方法
US8982654B2 (en) * 2013-07-05 2015-03-17 Qualcomm Incorporated DRAM sub-array level refresh
KR20160001098A (ko) * 2014-06-26 2016-01-06 에스케이하이닉스 주식회사 래치 회로 이를 포함하는 입출력 장치
US20180061484A1 (en) * 2016-08-29 2018-03-01 Apple Inc. Systems and Methods for Memory Refresh Timing
TWI639920B (zh) 2017-11-17 2018-11-01 財團法人工業技術研究院 記憶體控制器及其控制方法以及記憶體及其控制方法
TWI671632B (zh) 2018-10-24 2019-09-11 財團法人工業技術研究院 記憶體裝置及其復新資訊同步方法
CN112786084B (zh) * 2021-03-16 2023-06-23 北京时代全芯存储技术股份有限公司 记忆体装置

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JPH05109266A (ja) * 1991-10-17 1993-04-30 Sanyo Electric Co Ltd 半導体記憶装置
JP2988804B2 (ja) * 1993-03-19 1999-12-13 株式会社東芝 半導体メモリ装置

Also Published As

Publication number Publication date
JP2781350B2 (ja) 1998-07-30
US5511033A (en) 1996-04-23
GB2284692A (en) 1995-06-14
GB9422507D0 (en) 1995-01-04
JPH07226077A (ja) 1995-08-22
KR950014089B1 (ko) 1995-11-21
DE4439817C2 (de) 2002-03-14
KR950015374A (ko) 1995-06-16
DE4439817A1 (de) 1995-05-11
GB2284692B (en) 1998-04-08

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20131108