Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/4076—Timing circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

• the invention relates to a method for operating a semiconductor memory device according to the preamble of claim 1, and a semiconductor memory device according to the preamble of claim 7.
• ROM Read Only Memory or read only memory
• RAM Random Access Memory or read / write memory
• a RAM component is a memory in which you can save data after specifying an address, and later read out again at this address.
• the corresponding address can be entered into the RAM component via so-called address connections or address input pins; There are several for input and output of the data, e.g. 16 so-called data connections or data output pins (I / Os or input / outputs) are provided.
• a corresponding signal e.g. a read / write signal
• SRAM Static Random Access Memory
• DRAM Dynamic Random Access Memory
• the memory cells in particular DRAM components, the individual memory cells - arranged in a plurality of rows and columns next to one another - are arranged in a rectangular matrix or a rectangular array.
• multi-bank chip instead of one single arrays - several, for example four - essentially rectangular - individual arrays can be provided (so-called “memory banks”).
• ACT activate command
• memory bank assigned - (and by the row address (“Row-Address ”) defined) word line activated.
• a word line deactivation command for example a precharge command (PRE command)
• PRE command a precharge command
• ACT activate command
• RAS-CAS - delay there must be a certain time interval tRCD between the word line activation command (ACT command) and a corresponding read (or write) command (RD (or WT) command) (so-called RAS-CAS - delay).
• the RAS-CAS delay results e.g. from the time required by the sense amplifiers to amplify the data supplied by the memory cells addressed by the word line.
• the corresponding memory component control device (“memory controller”) - after the output of a corresponding word line activation command (ACT command) and a corresponding read- (or write) command (RD (or WT) command) - the respective word line is initially left in an activated state (ie the corresponding word line deactivation command (PRE command) is initially suppressed).
• ACT command a corresponding word line activation command
• RD read- (or write) command
• PRE command word line deactivation command
• the next access to the corresponding array is (a) memory cell ⁇ ) which is / are assigned to the same word line or line as that ( n) Memory cell ⁇ ) which was last accessed can be dispensed with the issuance of a further word line activation command (ACT command).
• ACT command word line activation command
• a corresponding read (or write) command can be output by the memory component control device (“memory controller”) to the respective array (“memory bank”) ( and the result is that the corresponding data are read out (or entered) immediately, without a corresponding RAS-CAS delay tRCD occurring.
• the object of the invention is to provide a novel method for operating a semiconductor memory component, as well as a new type of semiconductor memory component.
• Figure 1 is a schematic representation of the structure of a semiconductor memory device with multiple arrays, and a memory device control device according to an embodiment of the present invention
• FIG. 2 shows a schematic detailed illustration of the structure of a section of one of the arrays of the semiconductor memory component shown in FIG. 1;
• FIG. 3 shows a schematic detailed illustration of the construction of a partial section of the array section shown in FIG. 2;
• Figure 4 is a schematic timing diagram of signals used in the control of the arrays / sub-arrays shown in Figures 1, 2 and 3.
• FIG. 1 shows a schematic representation of the structure of a semiconductor memory component 1 or semiconductor memory chip, and a — central — memory component control device 5 according to an exemplary embodiment of the present invention.
• RAM Random Access Memory or random access memory
• DRAM Dynamic Random Access Memory or dynamic random access memory
• the address can be in several, e.g. two successive steps are entered (for example first a row address ("Row-Address”) - and possibly parts of a column address ("Colu ⁇ m-Address”) (and / or if necessary further address parts or parts thereof ( see below)), and then the column address ("Column Address”) (or the remaining parts of the column address (“Column Address”), and / or - only now - the above-mentioned further address parts ( or the other parts thereof) (see below), etc.).
• a corresponding control signal e.g. a ReaoV write signal
• a corresponding control signal e.g. a ReaoV write signal
• the data entered into the semiconductor memory component 1 are stored there, as will be explained in more detail below, in corresponding memory cells and later read out again from the corresponding memory cells.
• Each memory cell consists e.g. from a few elements, in particular only from a single, appropriately controlled capacitor, with the capacity of which one bit can be stored as a charge.
• a certain number of memory cells - each lying side by side in several rows and columns - are each arranged in a rectangular or square array (“memory bank”) 3a, 3b, 3c, 3d, see above that in an array 3a, 3b, 3c, 3d - depending on the number of memory cells contained - for example 32 MBit, 64 MBit, 128 MBit, 256 MBit, etc. can be stored.
• memory bank memory bank
• the semiconductor memory component 1 has a plurality, for example four, each of essentially identical construction, distributed uniformly over the surface of the component, and - controlled essentially independently of one another by the above-mentioned memory component control device 5 - Memory cell arrays 3a, 3b, 3c, 3d (here: the memory banks 0 - 3), so that a total memory capacity of, for example, 128 Mbit, 256 Mbit, 512 Mbit, or 1024 Mbit (or 1st GBit) for the semiconductor memory device 1.
• the above. (Entered into the semiconductor memory component 1 or the memory component control device 5) contains address - as part of the above. further address parts - a corresponding number (here, for example, two) bits (“array selection bits” or “bank address bits”) which are used to store the respective desired arrays 3a, 3b when storing or reading out data, 3c, 3d.
• each of the arrays 3a, 3b, 3c, 3d contains a certain number (for example between 10 and 100, in particular between 20 and 70, for example between 30 and 40, for example 32) sub-arrays 8a, 8b, 8c , 8d ("sub-banks" 8a, 8b, 8c, 8d).
• the sub-arrays 8a, 8b, 8c, 8d are each constructed essentially identically, are designed essentially rectangular, and each have a certain number of memory cells, each juxtaposed in several rows and columns.
• each two sub-arrays 8a, 8b, 8c, 8d (and between the sub-array 8a and an adjoining — here also essentially rectangular — decoding Z data amplifier area 11) are located here in each case likewise essentially each rectangular - reader amplifier areas 10a, 10b, 10c, 10d.
• a plurality of sense amplifiers are arranged in each of the reader amplifier regions 10a, 10b, 10c, 10d, with the corresponding sense amplifiers (or more precisely: those in the respectively between two different sub-arrays 8a , 8b, 8c, 8d the sense amplifier areas 10b, 10c arranged sense amplifiers) are each assigned two different sub-arrays 8a, 8b, 8c, 8d (namely the sub-arrays 8a directly adjacent to the corresponding reader amplifier area 10b, 10c) , 8b or 8c, 8d, etc.).
• the above-mentioned address (entered into the semiconductor memory component 1 or the memory component control device 5) contains - in contrast to conventional semiconductor memory components - as a further part of the above further address parts - a corresponding number (here, for example four) bits RA ⁇ 0: 4>("sub-array selection bits” or "sub-bank address bits"), which are used to save or read out data - within the by means of the arrays 3a, 3b, 3c, 3d specified by the "array selection bits” or "bank address bits” - the respectively desired sub-array 8a, 8b, 8c, 8d or the respectively desired sub-bank 8a, 8b , 8c, 8d.
• each array has an array control device 6a, 6b, 6c, 6d (BC or “which is separately assigned to the respective array 3a, 3b, 3c, 3d, here also essentially rectangular).
• bank control which is adjacent to the above-mentioned decoding Z data amplifier area 11, and a sub-array control area 7a, 7b, 7c, 7d (SBC or" sub- bank control ") is arranged in a corner area of the respective array 3a, 3b, 3c, 3d.
• Each of the sub-array control devices 9a, 9b, 9c, 9d is constructed essentially identically, and is configured essentially rectangular, and is adjacent to the respective sub-array control device 9a, 9b, 9c, 9d, respectively separately assigned sub-array 8a, 8b, 8c, 8d, and the two reader amplifier areas 10a, 10b, 10c, 10d assigned to it.
• a large number of word lines 12 run in each sub-array 8a, 8b, 8c, 8d (from the corresponding sub-array control device 9a, 9b, 9c, 9d) (in FIG. 2 is only for the sake of clarity only word line, namely the word line WL shown).
• the number of word lines 12 provided per sub-array 8a, 8b, 8c, 8d can correspond, for example, to the number of memory cell rows in the respective sub-array 8a, 8b, 8c, 8d (or, for example, for example with simultaneous readout / storage of each several, e.g. 2, 4, or 8 bits - corresponding to a fraction of this (e.g. half, a quarter, or an eighth)).
• the individual word lines 12 are arranged parallel to one another at equidistant intervals (and run parallel to the outer edge of the respective sub-array 8a, 8b, 8c, 8d).
• the MDQ lines 13a, 13b, etc. can - depending on the respective address - address any of the sub-arrays 8a, 8b, 8c, 8d contained in the respective array 3a.
• the individual MDQ lines 13a, 13b are arranged parallel to one another at equidistant intervals.
• the number of LDQ lines 14, 15 provided per reader amplifier area 10a, 10b (for example the number of further LDQ data lines (line 15, etc.) provided in the reader amplifier area 10a, and the number of LDQ lines (line 15, etc.) in the reader amplifier area.
• a further data lines LDQ (line 14, etc.), etc., provided in area 10b can typically be relatively small (eg 2 or 4).
• the length of a single (or partial) line section of the LDQ lines 14, 15 can essentially be a certain fraction of the length of the respective sense amplifier region 10a, 10b, e.g. approx. 1 / M (e.g. 1/16 or 1/32) of the respective sense amplifier area length.
• the individual LDQ lines 14, 15 of a specific reader amplifier region 10a, 10b are arranged parallel to one another at equidistant intervals. As can further be seen from FIG. 3, all of the LDQ lines 14, 15 located in a specific reader amplifier area 10a, 10b are via corresponding switches 16a, 16b (MDQ switches 16a, 16b) (here: via corresponding control lines) 17a, 17b controllable transistors 16a, 16b) are connected to the MDQ lines 13a, 13b assigned to the corresponding sense amplifier region 10a, 10b (or the corresponding sub-array 8a).
• MDQ switches 16a, 16b are connected to the MDQ lines 13a, 13b assigned to the corresponding sense amplifier region 10a, 10b (or the corresponding sub-array 8a).
• the corresponding switch 16a, 16b is closed or open (or here: the corresponding transistor 16a, 16b used as a switch - depending on the state of a control signal applied to the corresponding control line 17a, 17b - in a conductive or a blocked state), the corresponding LDQ line 14, 15 is conductively connected to, or electrically isolated from, the associated MDQ line 13a, 13b.
• the CSL lines 18 run parallel to the MDQ lines 13a, 13b, and perpendicular to the word lines 12, and the LDQ lines 14, 15.
• the individual CSL lines 18 are - at equidistant intervals (and in the essentially extending over the entire area of the respective sub-arrays 8a, 8b, 8c, 8d or reader amplifier areas 10a, 10b, 10c) - arranged parallel to one another.
• the number B of the CSL lines 18 can e.g. correspond to the number of memory cell columns in the respective array 3a or sub-array 8a, 8b, 8c, 8d (or, for example - for example with simultaneous readout / storage of several, for example 2, 4 or 8 bits - corresponding to a fraction thereof (e.g. half, a quarter, or an eighth)).
• the - central - memory component control device 5 (“memory controller”) can - as shown by way of example in FIG. 1 - be designed as a separate semiconductor component that communicates with the DRAM semiconductor memory component 1 via external pins.
• the memory component control device 5 can, for example, also be arranged on one and the same chip 1 as the above-mentioned memory cell arrays 3a, 3b, 3c, 3d (memory banks 0-3).
• a specific, fixed, special sequence of commands is run through in the exemplary embodiment shown here:
• the address - in particular the row address (“Row Address”) (and / or the column address (“Column Address”), and / or the “array selection bits” or “bank address”) bits ", and / or the” sub-array selection bits “or” sub-bank address bits ") - is assigned to a local one (located in or close to the respective array 3a, 3b, 3c, 3d) ) Cached memory device, and / or - in particular the row address ("Row-Address") - in a (in or near the sub-array control devices 9a, 9b, 9c, 9d associated with them) another memory device (on Intermediate storage of the address - in particular the row address ("row address”) - in a central storage device, for example in or near the memory component control device 5, can or must - as can be seen from the explanations below - to be dispensed with).
• an address expanded by the abovementioned "sub-array selection bits” or “sub-bank address bits” compared to conventionally used addresses can be transmitted in the present embodiment several corresponding (consecutive) word line or sub-array activate command signals (ACT signals) in each Array 3a, 3b, 3c, 3d (for example one after the other, in particular for example for successive clocks of the clock signal CLK) several - in different sub-arrays 8a, 8b, 8c, 8d one and the same array 3a, 3b, 3c, 3d - Word lines 12 or several different sub-arrays 8a, 8b, 8c, 8d of one and the same array 3a, 3b, 3c, 3d are brought into an activated state, and - in parallel - are left in the activated state (so that there are several, for example more than 2, 4, 8 or 10 sub-arrays 8a, 8b, 8c, 8d - or corresponding word lines - in an activated state
• sense ampHfier a large number of sense amplifiers (“sense ampHfier”) are arranged in each of the reader amplifier areas 10a, 10b, 10c, 10d of the respective array 3a, 3b, 3c, 3d, the corresponding sense amplifiers ( or more precisely: the sense amplifiers arranged in the reader amplifier regions 10b, 10c between two different sub-arrays 8a, 8b, 8c, 8d) are each assigned to two different sub-arrays 8a, 8b, 8c, 8d (notably each directly to the corresponding reader amplifier area 10b, 10c, adjacent sub-arrays 8a, 8b or 8c, 8d, etc.).
• word lines 12 are not activated - in parallel or simultaneously - which are two different but adjacent to one and the same sense amplifier region 10b, 10c
• Sub-arrays 8a, 8b are assigned, or - in parallel or simultaneously - sub-arrays 8a, 8b adjacent to one and the same sense amplifier region 10n, 10c (but only word lines in at most every second sub-array 8a, 8c , here for example at most in 16 sub-arrays 8a, 8c, or at most every second sub-array 8a, 8c).
• this word line or this sub-array is left in the activated state until access to a further word line of a further sub-array 8a, 8b (or to a further sub-array 8a, 8b), which is adjacent to one and the same sense amplifier area 10b, 10c, as the sub-array 8a, 8b of the - as explained above - activated word line (or the activated sub-array 8a, 8b).
• the word line or the sub-array 8a, 8b can then in the above-mentioned. activated state if later access to the same word line, or to a word line arranged in the same sub-array 8a, 8b, or to a word line which is arranged in the same array 3a, 3b, 3c, 3d, is to take place, as the activated word line or the activated sub-array 8a, 8b, but in a sub-array 8a, 8b, which does not adjoin one and the same sense amplifier area 10b, 10c as the activated sub-array 8a, 8b (or the sub-array 8a, 8b of the (as explained above - activated word line) - or if access to a word line of another array 3a, 3b, 3c, 3d is to take place.
• the memory component control device 5 of the semiconductor memory component 1 does not yet provide a corresponding word line or sub-array deactivation command which identifies the word line to be deactivated or the sub-array to be deactivated with a corresponding address Signal (pre-charge or PRE command signal) is sent.
• the corresponding ⁇ ) LDQ line (s) 15 is / are conductively connected (i.e. activated) to the associated MDQ line (s) 13a, 13b.
• the - relatively early - activation of the corresponding MDQ switch 16a ensures that - even with relatively large signal delay times - the corresponding ⁇ ) MDQ switch 16a in time - i.e. by the next clock CLK3 at the latest (or on the next, positive clock edge 23) - in the above closed or conductive state (see, for example, also the (first) state change 31 of the MDQ switch 16a illustrated in FIG. 4).
• the following clock CLK3 from the corresponding array control device 6a, 6b, 6c, 6d causes 18 corresponding control signals to be output on the corresponding CSL line (s), which are precisely specified by the corresponding column address ("Column Address”) (cf.
• the data output by the corresponding sense amplifier (s) are fed to the corresponding LDQ line (s) 15, and - via the corresponding MDQ switch (s) (closed as explained above) 16a - and the corresponding ⁇ ) MDQ line (s) to the above Decoder / data amplifier area 11 forwarded.
• the data (or the corresponding data signals) can optionally be further amplified and then output on the corresponding data pin (s) of the semiconductor memory component 1.
• a corresponding read or write command signal (Read- (RD- ) or Write (WT) command signal) is sent (which is stably connected to the corresponding control line at the corresponding clock edge 24) (here, for example, a "RD8c" signal which appeals to the sub-array 8c).
• the corresponding address in particular the address, can be sent out by the memory component control device 5 corresponding "array” and “sub-array selection bits", the row and column address, etc.
• the respective, separately for each array 3a, 3b, 3c, 3d provided for the array control device 6a, 6b, 6c, 6d receiving the respective RD (or WT) command signal (or alternatively: from the corresponding sub-array control device 9a, 9b, 9c, 9d), that the MDQ switch (or alternatively all MDQ switches) - defined by the column address ("Column Address") - of the - by the "sub-array selection bits" or "sub -bank address bits "- reader amplifier area 10c (or of the sub-area defined by the" sub-array selection bits "or” sub-bank address bits " Arrays 8c associated reader amplifier area 10c) closed or brought into a conductive state, ie is or are activated (for example by applying a corresponding control signal to the corresponding control line or lines).
• the MDQ switch or alternatively all MDQ switches
• the corresponding ⁇ ) LDQ line (s) 15 is or are conductively connected (ie activated) to the associated MDQ line (s) 13a, 13b (cf. for example also the state illustrated in FIG. 4) - Change 33 of the corresponding MDQ switch).
• the following clock CLK5 from the corresponding array control device 6a, 6b, 6c , 6d causes that on the or the corresponding - by the corresponding in the above Storage device stored column address ("Column Address") exactly specified - CSL line (s) 18 corresponding control signals are output (see, for example, the state change 51 of the corresponding signal shown in FIG.
• the data output by the corresponding sense amplifier (s) are fed to the corresponding LDQ line (s) 15, and - via the corresponding MDQ switch (s) (closed above) - and the Corresponding ⁇ ) MDQ line (s) forwarded to the above decoding Z data amplifier area 11. There the data (or the corresponding data signals) can be further amplified if necessary, and then on the corresponding data pin (s) of the Semiconductor memory device 1 are output.
• the corresponding address in particular the address, can be sent out by the memory component control device 5 corresponding "array” and “sub-array selection bits", the row and column address, etc.
• control signals output in response to the corresponding read (RD) or write (WT) command signal can - speaking similarly as described above in relation to the RD8a and the RD8c signal - are also only output a clock later (here: with clock CLK8) (cf., for example, the change in state 53 of the corresponding one - shown in FIG. 4 - dashed here shown - signal).
• CLK8 clock later
• the data output by the corresponding sense amplifier (s) are fed to the corresponding LDQ line (s) 15, and - via the corresponding MDQ switch (s) (closed above) - and the corresponding ⁇ ) MDQ line (s) to the above Decoder Z data amplifier area 11 forwarded.
• the data (or the corresponding data signals) can optionally be further amplified and then output on the corresponding data pin (s) of the semiconductor memory component 1.
• a corresponding word line or sub-array deactivation Command signal (PRE or pre-charge signal) is sent (and - for example at the same time - the corresponding address, in particular the "sub-array selection bits" or "sub-array bits” that specify the sub-array 8a, 8b to be deactivated.
• PRE sub-array deactivation Command signal
• the corresponding array control device 6a, 6b, 6c, 6d (or alternatively the corresponding sub-array Array control device 9a, 9b, 9c, 9d) causes the corresponding word line (or the corresponding sub-array 8a, 8b) to be deactivated, as a result of which the corresponding word line of the sub-array 8a, 8b, or the sub-array 8a, 8b, which adjoins one and the same sense amplifier area 10b, 10c, as the - now deactivated - sub-array 8a, 8b on the - in the next clock, the corresponding sub-array 8a, 8b addressing - the corresponding sub-array 8a, 8b or sub-array activation command (activate command (ACT)) is prepared.
• activate command activate command

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• 2003
  • 2003-08-28 DE DE10339665A patent/DE10339665B3/de not_active Expired - Fee Related
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