Classifications

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  • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/495—Lead-frames or other flat leads
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  • H01L23/495—Lead-frames or other flat leads
  • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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  • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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  • H01L2224/45001—Core members of the connector
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  • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
  • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
  • H01L2224/45144—Gold (Au) as principal constituent
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  • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
  • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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  • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
  • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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  • H01L2224/491—Disposition
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  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
  • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
  • H01L2224/85399—Material
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  • H01L24/42—Wire connectors; Manufacturing methods related thereto
  • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions

• the invention relates to a carrier device for a monolithically integrated circuit, the carrier device being encapsulated with the monolithically integrated circuit, the chip, by means of a thermoplastic.
• the plastic casing serves as the housing and the connecting legs which are coupled to the metallic carrier device and which are guided via bonding connections to the bonding contacts of the monolithically integrated circuit form the electrical housing connections.
• the reference potential of the monolithically integrated circuit which is generally the ground potential or a supply potential, is as homogeneous and undisturbed as possible so that this is achieved as well as possible in all operating states, most monolithically integrated circuits are not only connected to the reference potential via its back via the support platform, but the circuit itself is connected to the support platform via a large number of additional connections. This is usually done via bond connections from
• Bond contacts of the chip surface on the carrier platform To ensure that the bonding connections, which usually consist of gold wire, adhere well to the carrier platform made of copper, it is finished with a thin coating of silver, gold or another suitable material.
• Circuits with a high power consumption can reach crystal temperatures of up to 150 degrees Celsius and more during operation, while in the de-energized state the circuit assumes its ambient temperature, which can go down to -40 degrees Celsius in the automotive field, for example.
• the result is mechanical stresses between the individual materials because they have different coefficients of thermal expansion. This effect is exacerbated by the size of the monolithically integrated circuits. So shear forces occur between the individual layers of the housing, the chip and the carrier device. The shear forces that occur between the molding compound and the metallization layer of the carrier device are particularly dangerous because the adhesive forces there are relatively low and the thermal expansion of the metallic coating on the platform is very different
• Support platform no longer be led directly, but instead on platforms connected to the support platform.
• the platforms are elevated compared to the platform level and, due to their relatively steep flanks, form a mechanical fixed point in the area of the respective bond contacts with respect to lateral movements.
• the required height results from the elastic and plastic properties of the plastic and can be optimized in the experiment.
• a height that is approximately in the range of 1/10 of the chip height to the chip height itself is sensible.
• the pedestal is formed by a drawing or pressing process with a stamp-like tool in the frame production, then the height corresponds to approximately 1/10 of the material thickness of the carrier up to a maximum of its material thickness itself.
• flanks can be produced at an angle of more than 90 degrees, for example by undercut, a suitable crimping or a subsequent upsetting.
• the transitions at the upper and lower edge of the flank are also important, as they should have only minimal rounding radii, because otherwise a vertical component is added to the shear component, which promotes the lifting of the bond contacts on the pedestals again.
• the optimal flank height and its steepness which should be at least 45 degrees, are related.
• it is better for the Fixpun function if there are a large number of pedestals on the carrier device, even if not all pedestals are used for contacting.
• the podiums by themselves, i.e. without contacting them, are a suitable measure against others Disadvantages of delamination, for example, through which moisture can penetrate capillary into the housing.
• the platforms are on the edge of the support platform, it is possible to manufacture them by a kind of bending or folding device, for example by flanging special carrier areas at the edge of the platform.
• the presence of the platforms also facilitates selective finishing of the carrier device, e.g. by silvering or gilding.
• the finishing can more easily be restricted to the platforms due to the shape deviation of the platforms from the rest of the support platform, which means the rest
• Carrier device is spared from the finishing. In addition to saving material, this improves the overall adhesion of the plastic, because the copper oxide on the carrier surface has significantly better adhesion than the conventional finishing materials compared to the plastic.
• pedestals Another advantage of the pedestals is the reduction in the different heights when bonding the semiconductor crystal to the connection legs and the support platform.
• Fig. 2 shows in supervision a pedestal with multiple bonds
• FIG. 3 shows a top view of a carrier device with a chip and a plurality of pedestals.
• 1 schematically shows a detail of a cross section through a carrier device 1 with a platform 2.
• the cutting line runs through the platform 2, which is formed by means of a stamping tool during the frame production.
• the height hp of the platform with 120 micrometers is in the example shown about 1/3 of the carrier height h, which here has about 250 micrometers.
• the optimum of the platform height hp compared to the material thickness h of the carrier device 1 is approximately in a range from 1/5 to twice the material thickness h. Compared to the current crystal height of approximately 300 micrometers, this corresponds to a range of 1/10 of this crystal height up to 1.5 times the value.
• the platform In order for the platform to be suitable for multiple bonding, it must have a sufficient length and width, since about 35 micrometers plus a required bond spacing is required for each bond diameter.
• Bond wires 5 and 6 point in opposite directions. With this pedestal 2, two different chips can thus be connected to it on the support platform 1 shown in sections by means of multiple bonds.
• FIG. 3 finally shows a top view of a carrier device 1 designed as a platform with a single chip 7, which schematically represents a monolithically integrated circuit.
• the contacts from the chip 7 to the pedestals 2 are designed as multiple bonds. If the same carrier device 1 is used for different circuits, then it does no harm if some of the platforms 2, 2 'are not contacted. On the contrary, they represent additional fixed points that are even advantageous in the sense of the invention.
• the platform 2 ' is an example of a non-contact. it pedestal.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Wire Bonding (AREA)
• Lead Frames For Integrated Circuits (AREA)

Applications Claiming Priority (3)

Publications (1)

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Citations (2)

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• 2002
  • 2002-10-09 DE DE10247075A patent/DE10247075A1/de not_active Withdrawn
• 2003
  • 2003-10-06 KR KR1020057006068A patent/KR101003061B1/ko active IP Right Grant
  • 2003-10-06 WO PCT/EP2003/011006 patent/WO2004036646A1/de active Application Filing
  • 2003-10-06 US US10/531,141 patent/US20060151772A1/en not_active Abandoned
  • 2003-10-06 EP EP03775171A patent/EP1552558A1/de not_active Withdrawn
  • 2003-10-06 JP JP2004544075A patent/JP4550580B2/ja not_active Expired - Lifetime

Patent Citations (2)

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