JPH0621132A - 半導体装置とその製造方法 - Google Patents

半導体装置とその製造方法

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Publication number
JPH0621132A
JPH0621132A JP4177886A JP17788692A JPH0621132A JP H0621132 A JPH0621132 A JP H0621132A JP 4177886 A JP4177886 A JP 4177886A JP 17788692 A JP17788692 A JP 17788692A JP H0621132 A JPH0621132 A JP H0621132A
Authority
JP
Japan
Prior art keywords
die
semiconductor device
pad
bonding
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4177886A
Other languages
English (en)
Inventor
Tetsuo Yabushita
哲男 薮下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4177886A priority Critical patent/JPH0621132A/ja
Publication of JPH0621132A publication Critical patent/JPH0621132A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】 （修正有） 【構成】リードフレームのダイパッド６上に半導体素子
１を接着固定し、半導体素子のボンディングパッド２と
インナーリード３を金線４等のワイヤにて接続した後、
樹脂等で封止してなる半導体装置において前記ダイパッ
ド上に非絶縁物からなるダイポスト８を設置し、前記ボ
ンディングパッド２とワイヤ９にて接続した事を特徴と
した半導体装置。 【効果】グランドボンドを必要とする半導体装置におい
てダイパッドの大きさをグランドボンド無しの半導体装
置のダイパッドと同じくらいにできる。特にＱＦＰ等の
表面実装型半導体装置の高い信頼性を確保する事ができ
る。さらにはダイポストを使用する事で専用リードフレ
ームを使用する事無く半導体装置を製造でき、リードフ
レームの汎用性を高める事ができる。また銀メッキ範囲
を少なくしたリードフレームを使用できるという安価な
半導体装置を提供できる。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置とその製造方
法に係わり、さらに詳しくはパッケージの内部配線に関
するものである。
【０００２】
【従来の技術】図３は従来のグランドボンドを有する半
導体装置を一部断面で示した断面図である。図３におい
て半導体素子１の複数あるボンディングパッド２はイン
ナーリード３と金線４で接続される。又、半導体素子１
はダイパッド６の上に導電性樹脂７等を用いて接着固定
されている。グランドボンドはボンディングパッド２よ
りダイパッド６へグランドボンド用金線５で接続され
る。
【０００３】上記のようにグランドボンドが必要とされ
る半導体素子１は、ボンディングパッド２とダイパッド
６をグランドボンド用金線５で接続し、外部から電位を
得るためにボンディングパッド２とインナーリード３が
金線４で接続されるか、またはダイパッド６とインナー
リード３を分離せずそのままつなぎ外部入力端子へ接続
されるように形成されたリードフレームを用いて半導体
装置が製造される。
【０００４】
【発明が解決しようとする課題】上記のような従来のグ
ランドボンドを有する半導体装置においてはダイパッド
上にボンディングパッドからワイヤにてボンディングを
行っている。ところがワイヤをボンディングする為に
は、半導体素子を接着固定する為に用いられる樹脂を避
けてボンディングしなければならず、樹脂は半導体素子
を良好に固定するために半導体素子の回りに多めにはみ
出しており、それを避けるために半導体素子から離れた
箇所へボンディングする必要があった。その結果ダイパ
ッドサイズを大きくしなければならず、特にＱＦＰ等の
表面実装型半導体装置の信頼性を低下させるという課題
があった。又、ダイパッドへボンディングするためには
半導体素子の厚みの高さ分だけ金線を下へ落とさなけれ
ばならないため、半導体素子に近いところへボンディン
グすると金線と半導体素子がショートしてしまうという
課題があった。さらにはダイパッドとインナーリードを
分離せずそのままつながれたリードフレームを用いる
と、特定の半導体装置には利用できるがグランドボンド
を行わない半導体装置には利用できず専用化してしまう
課題があった。さらにはグランドボンドするためにダイ
パッドに通常銀メッキが必要となるが、コストダウンの
為に最近ではインナーリード部のみ銀メッキが施された
安価なリングメッキリードフレームが開発されたが、そ
れを利用できないという課題があった。
【０００５】本発明は上記の課題を解決するためになさ
れたもので、グランドボンドを必要とする半導体装置に
おいてダイパッドの大きさをグランドボンド無しの半導
体装置のダイパッドと同じくらいに出来、信頼性の低下
を防ぎ、かつリードフレームの汎用性を高める事が可能
な半導体装置とその製造方法を得る事を目的とするもの
である。
【０００６】
【課題を解決するための手段】リードフレームのダイパ
ッド上に半導体素子を接着固定し、半導体素子のボンデ
ィングパッドとインナーリードを金線等のワイヤにて接
続した後、樹脂等で封止してなる半導体装置において前
記ダイパッド上に非絶縁物からなるダイポストを設置
し、前記ボンディングパッドとワイヤにて接続し構成し
たものである。
【０００７】又、本発明に係わるダイポストの高さを半
導体素子の厚みの半分以上する事によりにさらに課題を
解決する方向となる。さらには、ダイパッドの固定方法
としては半導体素子をリードフレームに固定するのと同
じ方法、つまり樹脂接着または金属間共晶にて行う事で
構成されている。
【０００８】
【実施例】図１は本発明の一実施例の断面図である。半
導体素子１は導電性樹脂７を介してダイパッド６に接着
固定されている。半導体素子１のボンディングパッド２
はインナーリード３と金線４によって接続されている。
グランドボンドは他のボンディングパッド２からダイポ
スト８にグランドボンド用金線９によって接続される。
ダイポスト８は導電性樹脂７を介してダイパッド６と接
続されている。ダイポスト８の材質として構成材料の熱
ストレスでの信頼性を考慮した場合、熱膨張係数が合っ
た材料が望ましくダイパッド６と同じか半導体素子１と
同じである事がより信頼性の高い半導体装置を提供する
事になる。ダイポスト８のダイパッド６への接続は半導
体素子１をダイパッド６へ接着固定する際塗布される導
電性樹脂７の範囲を部分的に広げるか、または後で塗布
し、導電性樹脂７の硬化前に接着固定する方が工程の簡
素化ができる。又、ダイポスト８に半導体素子１と同じ
材料を用いた場合ダイポスト８とダイパッド６の固定に
金ーシリコン共晶等の金属間共晶を用いてより強固な固
定ができる。さらに導電性樹脂７や金属間共晶固定では
ダイパッド６上に銀メッキは不要で、グランドボンドに
おいてもダイポスト８上にボンディングを行うためダイ
パッド６上に銀メッキが不要となり安価なリングメッキ
リードフレームを用いる事が可能となる。又、ダイポス
ト８の高さは半導体素子１の厚みと同程度か半分位の高
さまでが一番良くこれによりグランドボンディング用金
線９を下へ落とさなくても良くなり半導体素子１とのシ
ョートの危険性を考慮せずに問題なくボンディング可能
となる。
【０００９】図２は本発明の他の実施例の平面図であ
る。複数のグランドボンドが必要な場合細長いダイポス
ト８を用い複数のボンディングパッド２よりダイポスト
８にグランドボンド用金線９によって接続される。
【００１０】
【発明の効果】以上説明したように、本発明によればダ
イポストを設置する事によりグランドボンドが必要な半
導体装置に於いても不必要な半導体装置と同程度のダイ
パッドサイズを得る事ができる事によってＱＦＰ等の表
面実装型半導体装置の高い信頼性を確保する事ができ
る。さらにはダイポストを使用する事で専用リードフレ
ームを使用する事無く半導体装置を製造でき、また銀メ
ッキ範囲を少なくしたリードフレームを使用できるとい
う安価な半導体装置を提供する効果を有する。
【図面の簡単な説明】
【図１】本発明の一実施例の断面図である。
【図２】本発明の他の実施例の平面図である。
【図３】従来のグランドボンドを有する半導体装置の断
面図である。
【符号の説明】
１ ・・・半導体装置 ２ ・・・ボンディングパッド ３ ・・・インナーリード ４ ・・・金線 ５、９・・・グランドボンディング用金線 ６ ・・・ダイパッド ７ ・・・導電性樹脂 ８ ・・・ダイポスト

Claims (6)

    【特許請求の範囲】
  1. 【請求項１】 リードフレームのダイパッド上に半導体
    素子を接着固定し、半導体素子のボンディングパッドと
    インナーリードを金線等のワイヤにて接続した後、樹脂
    等で封止してなる半導体装置において前記ダイパッド上
    に非絶縁物からなるダイポストを設置し、前記ボンディ
    ングパッドとワイヤにて接続したことを特徴とする半導
    体装置。
  2. 【請求項２】 請求項１記載の半導体装置において、ダ
    イポストの高さが半導体素子の厚みの半分以上であるこ
    とを特徴とする半導体装置。
  3. 【請求項３】 請求項１記載の半導体装置において、ダ
    イポストの材質がリードフレームと同じであることを特
    徴とする半導体装置。
  4. 【請求項４】 請求項１記載の半導体装置において、ダ
    イポストの材質が半導体素子と同じであることを特徴と
    する半導体装置。
  5. 【請求項５】 請求項１記載の半導体装置において、ダ
    イポストとダイパッドの固定を、半導体素子とダイパッ
    ドの接着固定方法と同じ方法で行うことを特徴とする半
    導体装置の製造方法。
  6. 【請求項６】 請求項１記載の半導体装置において、ダ
    イポストとダイパッドの固定を、金属間共晶にて行うこ
    とを特徴とする半導体装置の製造方法。
JP4177886A 1992-07-06 1992-07-06 半導体装置とその製造方法 Pending JPH0621132A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4177886A JPH0621132A (ja) 1992-07-06 1992-07-06 半導体装置とその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4177886A JPH0621132A (ja) 1992-07-06 1992-07-06 半導体装置とその製造方法

Publications (1)

Publication Number Publication Date
JPH0621132A true JPH0621132A (ja) 1994-01-28

Family

ID=16038781

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030091519A (ko) * 2002-05-28 2003-12-03 삼성전기주식회사 접지와이어 본딩 벽을 갖는 파워 앰프 모듈 및 파워 앰프모듈 기판 제조방법
WO2004036646A1 (de) * 2002-10-09 2004-04-29 Micronas Gmbh Trägereinrichtung für monolithisch integrierte schaltungen
KR100708051B1 (ko) * 2001-07-28 2007-04-16 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP2008066553A (ja) * 2006-09-08 2008-03-21 Furukawa Electric Co Ltd:The 半導体装置
CN104752383A (zh) * 2015-04-15 2015-07-01 江苏晟芯微电子有限公司 一种新型半导体防脱落封装结构

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100708051B1 (ko) * 2001-07-28 2007-04-16 앰코 테크놀로지 코리아 주식회사 반도체패키지
KR20030091519A (ko) * 2002-05-28 2003-12-03 삼성전기주식회사 접지와이어 본딩 벽을 갖는 파워 앰프 모듈 및 파워 앰프모듈 기판 제조방법
WO2004036646A1 (de) * 2002-10-09 2004-04-29 Micronas Gmbh Trägereinrichtung für monolithisch integrierte schaltungen
JP2006503427A (ja) * 2002-10-09 2006-01-26 ミクロナス ゲーエムベーハー モノリシック集積回路用の支持装置
JP2008066553A (ja) * 2006-09-08 2008-03-21 Furukawa Electric Co Ltd:The 半導体装置
CN104752383A (zh) * 2015-04-15 2015-07-01 江苏晟芯微电子有限公司 一种新型半导体防脱落封装结构
CN104752383B (zh) * 2015-04-15 2017-08-08 苏州聚达晟芯微电子有限公司 一种新型半导体防脱落封装结构

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