JPS59104148A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS59104148A
JPS59104148A JP57213556A JP21355682A JPS59104148A JP S59104148 A JPS59104148 A JP S59104148A JP 57213556 A JP57213556 A JP 57213556A JP 21355682 A JP21355682 A JP 21355682A JP S59104148 A JPS59104148 A JP S59104148A
Authority
JP
Japan
Prior art keywords
resin
leads
lead
semiconductor element
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57213556A
Other languages
English (en)
Inventor
Yoshiyuki Minamiguchi
南口　義之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57213556A priority Critical patent/JPS59104148A/ja
Publication of JPS59104148A publication Critical patent/JPS59104148A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明はプラスチック樹脂で封止する半導体装置の改良
に関する。
従来のプラスチック樹脂で封止する半導体装置は第１図
に示すように各電極リードを同一平面にそろえるリード
フレーム形状を用いているのが一般となっている。この
リードフレームの作成は巻線状にした金桝板を金属打抜
き金型によシ高圧力高速にて連続打抜きで加工している
。リードフレームを成る一定の長さに切断し、コレクタ
リード基板１上に半導体素子４を金属半田６（例えば、
金合金）にて高熱マウントロウ付をする。半導体素子４
０ベース、エミッタ接続は金属細線５（例えは、金線）
にてそれぞれベースリード基板２とエミッタリード基板
３とにボンディング接続する。
その後高熱高圧力によ）プラスチック樹脂を溶融し、個
々の半導体装置を樹脂７にて封止し、コレクタリード基
板１、ベースリード基板２、エミッタリード基板３の根
元を切断し完成する（第２図）。
近年該半導体装置を使用する実装回路基板の集積度を増
し且つ小型化に移行したため、該半導体装置も小型化に
なった。しかしながら、半導体装置が小型化になっても
半導体素子（即ちチップ）４の大きさに大幅に変わりが
ないためコレクタリード基板１の大きさは従来と同じで
樹脂７の外形寸法のみ大幅に小さくなっている。従って
コレクタリード基板１の単位面積当りの樹脂７の量が従
１ 来よりＨから１の減少となった。。
一方、従来の半導体Ｍｔｖコレクタリード奮板１に与え
ていたリードフレーム製作時の金属打抜き金型による打
抜きストレスや、半導体素子４を金属半田６にて高熱マ
ウントロウ付する際に起きる熱ストレス等のストレスが
歪みとなりコレクタリード基板１に残存していた。これ
らの残存歪みは半導体装置を小型化したときでも同じで
ある。
しかも半導体装置のコレクタリード基板１０単位１ 面積当シの樹脂７の量が百から１の減少になったため、
これまで樹脂７内で押えられていたコレクタリード基板
１の歪みによる変形は樹脂量が減少したために急激に顕
著になってきた（第３図）。
とくにチップ搭載部となるコレクタリード基板１が変形
し易く、それによって半導体素子４に大きなストレスが
加わり素子のクラック現象とか、金属紺ｌＩＭ５の断線
等の致命的な不良の発生が多くなってきた。又、リード
の変形（反シ）によって樹脂自体にもクラックが生じ気
密性が悪くなるという現象も起きてきた。
従って本発明の目的はリードに変形防止加工を施した半
導体装置を提供することにある。
本発明の半導体装置はリードの表面にその変形方向に対
して直角方向に細長い突起を設けたことを特徴とし、と
くに面積の広いチップ搭載リードに対してこの加工を施
こすと効果がある。又、突起はチップをはさむように複
数個設けた方が効果は大きい。突起形成法としてはエツ
チング加工、プレス加工、あるいはロウ付等適宜任意に
使用してよい、。
本発明によればリードフレーム形成時の機械的圧力やチ
ップマウント時あるいは樹脂封止時の熱加工に対してリ
ードの変形が有効に防止され、ボンディング不良やチッ
プクラックはもとより、マウントはがれや樹脂クランク
をも効果的に防止できる。
以下図面を参照して本発明の一実施例を詳細に説明する
。
第４図（ａ）Φ）は夫々本実施例の正面からみた内部構
成図と側面からみた内部構成図である。図よシ明らかな
ようにこの実施例では、半導体素子（チップ）１４が金
属半田合金（ろう材）６でマウントされるコレクタリー
ド１１（この場合素子からの発熱も大きい）に対して、
チップの両側に突起８．１８をリードの幅方向に長く設
けている。。
１２．１３は夫々エミッタおよびベースリードで、１５
はボンディング金線、１７は樹脂である。この例によれ
ば、コレクタリード１１上に機械的又は化学的処理で設
けた突起線によって、素子σ）クラックやボンディング
線の断線および樹脂のクラックを防止でき、樹脂量を減
らしても致命的な不良は生じない。
なお、突起線は１本以上何本でもよい。
【図面の簡単な説明】
第１図は巻線状にしだ金槁板を金属打抜き金型により高
圧力、高速にて連続打抜きで製作し一定の長さで切断し
たリードフレームの平面図、第２図（ａ）（ｂ）は夫々
従来のプラスチック樹脂に封止込まれた半導体装置の正
面図と側面図であり、第３図はコレクタリード基板の歪
みによる変形を示めす断面図、第４図（ａ）（ｔ））は
夫々本発明の一実施例によるプラスチック樹脂に封止込
まれた半導体装置の５− 正面図と側面図である。 １．１１・・・・・・コレクタリード基板、２．１２・
・・・・・ベースリード基板、３．１３・・・・・・エ
ミッタリード基板、４．１４・・・・・・半導体素子、
５．１５・・・・・・金属組線（金線）、６．１６・・
・・・・金属半田（金合金）、７．１７・・・・・・プ
ラスチック樹脂、８．１８・・・・・・突起線。 ６− Ａ覧ｌ　凹 − 第２日 第３図 草４目 ２１９

Claims (1)

    【特許請求の範囲】
  1. 少々くとも半導体素子をマウントするリードの表面に、
    幅方向に突起を形成したことを特徴とする半導体装Ｒ８
JP57213556A 1982-12-06 1982-12-06 半導体装置 Pending JPS59104148A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57213556A JPS59104148A (ja) 1982-12-06 1982-12-06 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57213556A JPS59104148A (ja) 1982-12-06 1982-12-06 半導体装置

Publications (1)

Publication Number Publication Date
JPS59104148A true JPS59104148A (ja) 1984-06-15

Family

ID=16641158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57213556A Pending JPS59104148A (ja) 1982-12-06 1982-12-06 半導体装置

Country Status (1)

Country Link
JP (1) JPS59104148A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004036646A1 (de) * 2002-10-09 2004-04-29 Micronas Gmbh Trägereinrichtung für monolithisch integrierte schaltungen

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004036646A1 (de) * 2002-10-09 2004-04-29 Micronas Gmbh Trägereinrichtung für monolithisch integrierte schaltungen

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