EP0000897A1 - Procédé de fabrication de régions de silicium isolées latéralement - Google Patents

Procédé de fabrication de régions de silicium isolées latéralement Download PDF

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Publication number
EP0000897A1
EP0000897A1 EP78100614A EP78100614A EP0000897A1 EP 0000897 A1 EP0000897 A1 EP 0000897A1 EP 78100614 A EP78100614 A EP 78100614A EP 78100614 A EP78100614 A EP 78100614A EP 0000897 A1 EP0000897 A1 EP 0000897A1
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EP
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Prior art keywords
grooves
silicon
etching
layer
range
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EP78100614A
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German (de)
English (en)
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EP0000897B1 (fr
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James Allan Bondur
Hans Bernhard Pogge
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/168—V-Grooves
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Definitions

  • the invention relates to a method for producing laterally insulated regions in a silicon body, in which grooves at the locations at which the insulation frame is to be formed are etched into the silicon by means of reactive ion etching, then thermally oxidized on the surface and then filled with dielectric material.
  • the dielectric materials that have been used are silicon dioxide, glass, etc.
  • the preferred isolation for these active devices and circuits is any type of dielectric isolation.
  • the dielectric isolation has a significant advantage over the isolation by means of a P / N junction in that it allows the circuit elements to abut the isolation, which enables a greater packing density of the active and passive components on the chip with the integrated circuits.
  • One type of dielectric isolation includes the formation of grooves or depressions at the locations in silicon where the isolation areas are to be formed. While the formation of the grooves, the rest of the silicon surface is protected by a protective film which is practically not attacked by the silicon etchant which is used to produce the grooves.
  • the usual protective film consists of a double layer made of silicon nitride and silicon dioxide. After the formation of the grooves by means of the usual chemical etching, the silicon body is subjected to a well-known oxidation step, the silicon being oxidized in the region of the groove and, on the one hand, the groove being filled with silicon dioxide and, on the other hand, the remaining silicon regions being further apart.
  • One of the main problems with this process is known as "bird's beak".
  • the "bird's beak” is a non-planar structure made of silicon dioxide, at the upper edge of the groove, and is caused by the lateral oxidation of the silicon under the silicon nitride layer. Since the silicon dioxide formed takes up about twice the space during the oxidation of silicon, and since the silicon nitride limits the unrestricted expansion of the resulting oxide material, the silicon nitride is pushed upwards at the edge of the groove. This phenomenon ultimately results in mechanical stresses in the immediate vicinity of the groove and, moreover, difficulties in subsequently creating diffusion-doped regions which directly abut the vertical part of the silicon dioxide. Because of this difficulty in direct bumping, there is no substantial benefit hoped for by the silica area. This method described above is described more fully and in more detail in U.S. Patents 3,970,486, 3,534,234 and 3,648,125 and in German Patent Application No. 22 18 892.
  • an epitaxial layer is very much dependent on the area ratio of silicon dioxide regions to silicon regions.
  • the semiconductor material would grow at different speeds on two silicon regions of different sizes, so that at the end of the method step the epitaxial layer in these regions is of different thickness.
  • mesa structures there is also a tendency to form crystallographic facets. This results in a pyramid-like growth and leads to a widening of the isolation areas, which cannot be corrected using lithographic means.
  • the sloped interface between the silicon and the silica also makes it difficult to reliably cause diffused areas to collide with the silica area.
  • the method according to the invention it is possible to fill the grooves with an insulating material which has a high dielectric constant and a high density and has no interfering inclusions. This is essentially achieved in that the grooves taper with the depth in a fixed manner, which enables the grooves to grow practically unhindered by the geometry.
  • an upper surface of the dielectric is obtained Material in the grooves which is substantially coplanar with the surface of the silicon body.
  • Reactive ion etching is advantageously carried out in such a way that a reactive gas is used which consists of a material containing a halogen from the group chlorine, bromine, iodine or one of these elements and the reaction atmosphere in amounts in the range between about 2 and about 10% is added to work at a pressure in the range between about 2 and about 50 pm Hg and to set the etching rate to a value in the range between about 0.03 and 0.08 pm / mine.
  • etching takes place at a power density in the range between approximately 0.1 and approximately 0.75 W / cm 2 .
  • the method according to the invention is also particularly advantageous when a silicon body is used which contains at least one highly doped layer and the grooves are etched so deep that they essentially penetrate the highly doped layer. If such a highly doped layer is present, it is difficult, even with reactive ion etching, to avoid severe undercutting in the lateral direction, which poses problems if a particularly high packing density of the semiconductor components is required. A particularly slight undercut is obtained if chlorine is used as the reactive gas when carrying out the process according to the invention and this is mixed in amounts between about 2 and about 8% of the reaction atmosphere.
  • a photoresist mask formed in accordance with the desired pattern of the grooves is produced in a known manner on an SiO 2 layer applied to the silicon body in order to produce a fixed taper angle, if the SiO 2 layer is then reactively etched so that the etching speed ratio from Si0 2 to photoresist is approximately one and that the silicon is then etched using the SiO 2 mask in such a way that the etching speed ratio of Si: Si0 2 is not too high.
  • the taper angle is understood to mean the angle which the side wall of a groove which tapers with the depth forms with the vertical. In the known manufacturing processes for photoresist masks, mask windows are obtained which taper with the depth.
  • the grooves extend into a P-type area, it is advantageous in order to prevent inversion to implant impurities which impart P-conductivity in an amount in such an amount that locally an area in the bottom area of the grooves prior to thermal oxidation of the P + type arises.
  • F ig. 1A includes the monocrystalline silicon substrate 10, which for illustration purposes is referred to as belonging to the P type, an N + type layer 12 deposited on the substrate 10 and a layer 14 deposited on the layer 12 with an N - Conductivity.
  • the invention is also applicable if all or some of the layers 10, 12 and 14 were of a conductivity type opposite to that indicated.
  • layer 12 preferably consists of a region with high conductivity so that it can take over the function of the collector of a bipolar transistor in the final structure. This structure can be created using various manufacturing processes.
  • the preferred technique is to start from a single crystal P - type silicon substrate and then to introduce an impurity, for example arsenic, antimony or phosphorus, which generates an N type conductivity over the entire surface into the silicon substrate by means of diffusion or ion implantation.
  • an impurity for example arsenic, antimony or phosphorus
  • Layer 14 is then grown on layer 12 by epitaxy. This can be done using known methods, for example, by allowing mixtures of SiCL 4 and H 2 or SiH 4 and H 2 to act on the substrate at temperatures in the range between about 1000 and about 1200 ° C.
  • the N + type layer has a typical thickness in the range between approximately 1 and 3 ⁇ m, while the epitaxial layer has a thickness in the range between approximately 0.5 and 10 ⁇ m, the exact thickness of the component to be produced being depends.
  • the structure could be produced using various combinations of thermal diffusion, ion implantation and / or epitaxial growth.
  • FIG. 1A and 1B relate to the etching of openings or channels in the silicon structure, which taper with the depth, by means of reactive ions.
  • a silicon dioxide layer 16 is produced by known methods, ie either by means of thermal growth at a temperature of 970 ° C. in a wet or dry oxygen atmosphere or by means of chemical precipitation from the vapor phase. Other mask materials such as silicon nitride or aluminum oxide or combinations of these materials etc. can also be used.
  • the openings 18 are created in the oxide layer in the areas in which dielectric insulation is desired. These openings are created using standard photolithography and etching techniques.
  • the structure shown in FIG. 1A is now prepared for the etching process using reactive ions.
  • the plasma excited with high frequency exists, as in that Laid-open specification is made of a material containing reactive chlorine, bromine or iodine.
  • the thickness of the masking layer 16 is in the range between approximately 0.2 and 2 ⁇ m, the exact thickness depending on the required depth of the hole or groove to be produced in the silicon.
  • the precise description of the high-frequency discharge device is given in the aforementioned publication.
  • the atmosphere during reactive ion etching or the plasma atmosphere preferably consists of a combination of an inert gas, such as argon with a material containing chlorine.
  • a power density in the order of about 0.1 to 0.75 W / cm 2 generated by means of a high-frequency voltage source causes reactive ion etching of the silicon, in which the silicon is removed at a speed in the range between about 0.02 and about 0.08 ⁇ m per minute becomes.
  • the desired etch result is shown in FIG. 1B, in which it can be seen that the openings or channels at least partially penetrate the region 10 of the P conductivity type. In any case, the channels or openings largely pass through the region 12 of the N + type.
  • the openings or channels taper at least so much in depth that the angle between the opening wall and the vertical is greater than about 2 °. This is necessary because in the subsequent process step of filling with dielectric material, the deposition near the upper edge of the groove takes place somewhat more quickly than at the bottom of the groove. If one assumed holes or grooves with vertical walls, the narrow hole still present would eventually grow near the upper edge of the hole during the deposition, with the result that the dielectric material in the area under the overgrown area bad quality. In the case of a groove that tapers to a sufficient extent with the depth, the groove becomes its own Bottom filled.
  • the preferred degree of taper which is suitable for suitable filling with dielectric material, such as silicon dioxide, by means of chemical vapor deposition, will depend in part, as will become clear when discussing FIG. 6, on the groove width.
  • a taper angle which is greater than 20 °, takes up an unnecessarily large area on the surface of the semiconductor component. This formation of the structure with the tapering grooves or holes depends mainly on two factors. The first factor is the angle of the side wall of the opening 18 in the masking layer 16. The second factor is the difference in the speeds at which the mask material and the substrate material are etched. The higher the ratio of the speeds at which the substrate material and the mask material are etched, the more vertical the hole walls in the silicon substrate become.
  • openings are generally obtained in the photoresist, which taper somewhat with the depth. If reactive ion etching is then used to create openings in the underlying silicon dioxide film through the tapered windows in the photoresist, and if the ratio of the speed of the lacquer etching to that of the silicon dioxide etching is approximately one, the tapering present in the lacquer window is applied to the window in the Transfer silica. As a result, this taper is then transferred to the silicon unless a high ratio of the silicon etching speed to that of the silicon dioxide etching is set.
  • the taper in the silicon dioxide mask is preferably in the taper angle range between 5 and 20 °.
  • the windows in the silicon dioxide will also have vertical perforated walls and it is the case under these conditions that the openings will also have vertical hole walls in silicon, regardless of the ratio of the speed of silicon etching to the speed of silicon dioxide etching.
  • etch rates also affects the undercutting of highly doped N + or P + type areas, such as area 12.
  • etch rates of approximately 0.07 pm per minute holes with vertical holes become in N + type areas Walls without lateral undercut.
  • Fig. 2 is a graph showing the influence of the silicon etching rate in pm per minute as a function of the percentage of chlorine-containing material in argon for various pressures in the reaction chamber.
  • Curve 20 shows the conditions at a pressure of 10 pm Hg. At this pressure and at the specified etching speeds, there is practically no undercutting in the N + type regions, it being irrelevant what the percentage of the chlorine-containing material is.
  • curve 20 shows that when the content of the chlorine-containing material in argon changes from 10% to about 3%, the taper angle in the holes changes from about 0 to about 20 °.
  • the power is 0.16 W / cm and the cathode is made of silicon dioxide.
  • Curve 22 shows that a groove with vertical walls is obtained at an etching rate of 0.06 pm per minute and a chlorine content in argon of approximately 3%. If one moves upwards on the curve to an etching rate of 0.10 pm per minute and a content of the chlorine-containing material in argon of 5%, one can see the undercutting in the area of the N + type.
  • Curve 24 shows the situation at a pressure of 40 pm Hg. With a content of the chlorine-containing material in argon of 2% and an etching rate of 0.06 pm per minute, undercutting in the N + range is not a problem. However, if you move up the curve up to an etching rate of 0.08 pm, the undercut begins to become clear. It can be assumed that if you move further up the curve, the undercutting becomes even stronger. At point 26 the relationship is shown at a total pressure of 90 ⁇ m Hg.
  • the main problem that follows from underetching the N + region is that it limits the minimum distance that two isolation regions can have from each other. If a very strong undercut occurs and two isolation areas are very close together, the area 14 will fully undercut. In addition, the N + collector region will be completely removed so that no transistor can be formed. Yet another problem will arise in each undercut area in that the non-linearly tapering holes are not clean with dielectric material that is vapor-deposited by chemical deposition. such as silicon dioxide. The result is a filled groove that contains a buried hole or channel.
  • the openings or channels are thermally oxidized by exposing the semiconductor body to an oxidizing atmosphere, for example a moist oxygen atmosphere at 970 ° C.
  • the semiconductor body is exposed to the atmosphere for between about 10 and about 30 minutes to create the preferred silicon dioxide thickness within the opening or channel.
  • the preferred thickness is between about 0.05 and about 0.2 pm.
  • the purpose of the thermal oxide 30 is to ensure good properties of the interface between the silicon and the silicon dioxide. Dielectric material that has been applied by chemical vapor deposition generally does not have as good properties as thermally grown oxide. Dielectric material with good properties is necessary, however, to allow diffused P / N junctions to subsequently hit the dielectric insulation.
  • the minimum thickness must be nominally 0.05 ⁇ m in order to have a good thermal silicon dioxide layer. A thinner layer could cause difficulties in having through pores in the oxide and could cause problems with electrical integrity.
  • the maximum thickness is mainly determined by the time it takes to grow at elevated temperatures. Long growth times at high temperatures mean that each diffused P / N transition moves in the silicon areas. Very thick oxide films, which at such temperatures have also created stress problems in the silicon material.
  • the thermally grown oxide 30 follows the tapering of the side walls of the opening almost exactly, which has been produced by means of reactive ion etching.
  • the result of the next process step, in which the openings are filled with a suitable dielectric material, is shown in FIG. 1D, from which it can be seen that the opening or the channel has a layer 32 consisting of silicon dioxide produced by means of precipitation from the vapor phase is filled.
  • the preferred filling process is a chemical deposition of silicon dioxide from the vapor phase at 800 to 1000 ° C using gas mixtures containing C0 2 , SiH 4 and N 2 or N 2 0, SiH 4 and N 2 .
  • Typical deposition rates are between 5 and 10 nm / min. and the total thickness of the deposited layers is nominally 3 pm for 2 ⁇ m wide grooves if an approximately planar surface is desired.
  • the specific relationship between the flatness and the thickness of the silica deposited by chemical vapor deposition is shown in FIG. 8.
  • FIGS. 3, 4 and 5 illustrate the progressive filling of the grooves by means of a series of lines which represent the same layer thickness ranges from silicon dioxide deposited by chemical vapor deposition.
  • the etched gap area 40 tends to be buried further down in the filled groove as the groove width widens and the taper angle increases.
  • Fig. 4 shows the influence of the taper angle using grooves of the same width.
  • FIG. 6 contains experimental data which show the change in the taper angle (denoted by 1 a in FIG. 6) of the hole wall with the progressive filling of the groove. It is obvious that if one starts with grooves with vertical walls, one obtains grooves with a negative taper angle, which consequently results in cavities in the silicon dioxide.
  • Figure 9 shows similar experimental data, i.e. 8, and emphasizes that the planarization depends strictly on the width of the groove and not on the taper angle a.
  • the final step of the process is reactive ion etching of the silicon dioxide layer 32 shown in FIG. 1D, producing the structure shown in FIG. 1E.
  • the excess of silicon dioxide is conveniently removed by reactive ion etching and with the aid of an optical film thickness measurement system or if the speed at which the silicon dioxide is etched is known, even without such a system.
  • the device used for this process step preferably consists of a device for sputter etching at low pressure, in which the plate is positioned on a cathode cover plate made of silicon.
  • a fluorinated hydrocarbon such as CF 4 can be used as the etchant, because then the ratio of the speed of SiO 2 etching to that of Si etching is approximately 1: 1.
  • the gas pressure can be in the range between 10 and 70 pm Hg and the gas flow in the range between 2 and 50 ccm / min.
  • the high-frequency power level is preferably in the range between approximately 0.1 and 0.5 W / cm 2 .
  • the result of thinning the silicon dioxide layer by means of reactive ion etching may make the insufficiently buried region of poor oxide visible in the center of the groove. This is a potential problem because any wet etch of the wafer surface, if such areas of poor silica are exposed, would cause a gap to form in that area. Such gaps could become potential traps for dirt or process residues, and could negatively affect the properties of the component.
  • An alternative method to avoid some of the undercutting problems would be to fabricate a highly doped region 12 in such a way that this region is interrupted or has recesses where the openings or channels are to be formed. In this case, a weakly doped region of the P type would surround the region which is to be etched by means of reactive ions.
  • This alternative requires special oxidation, photolithography and etching steps to create this N + type region with gaps.
  • Forming a P + -type region below the isolation region can be useful if the substrate is P-type. In such cases, the P region tends to change its resistance, which can go so far as to invert the material from which it is thermally oxidized into an N-type one.
  • a P + area prevents such an inversion possibility.
  • Such a region can be created by introducing a dopant, such as boron, by means of ion implantation before the thermal oxidation of the groove. The best way to do ion implantation is to cover the groove with a thin layer of silicon dioxide created by chemical vapor deposition.
  • Such a covering between approximately 50 and 80 nm thick allows implantation of, for example, boron through the bottom of the groove into the silicon but not through the silicon dioxide on the side walls of the groove. This is because the ion beam forms an acute angle with the side walls of the groove and therefore the distance through the silicon dioxide to the silicon is greater than the real thickness of the silicon dioxide.
  • Another possibility of modifying the fabrication process is to subject the semiconductor substrates to a tempering step in a water vapor atmosphere after the process step in which the structure shown in FIG. 1E is formed.
  • This tempering which is carried out at a temperature in the range between 900 and 950 ° C. any poor quality exposed silica in the central region of the groove is converted to good quality silica.
  • the advantage of this process modification is that when it is used it is no longer so important that the areas of poor quality silica are buried with certainty and it is therefore no longer so important that the taper angles are as large as possible, which is why it is possible to provide a higher component density in the manufacture of integrated circuits.
  • the process modification it is possible, for example, poor quality silicon dioxide, which in the presence of small taper angles, such as. B. such in the range between 2 and 4 °, to convert into good quality.
  • the method according to the invention is not restricted to the applications described in the exemplary embodiments.
  • the single-crystalline silicon regions produced by means of the described method can also be used to form components other than bipolar transistors.
  • Such components would be passive components such as Resistors and active components such as Include metal oxide silicon field effect transistors (MOSFET) devices.
  • MOSFET include metal oxide silicon field effect transistors

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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EP78100614A 1977-08-15 1978-08-07 Procédé de fabrication de régions de silicium isolées latéralement Expired EP0000897B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/824,361 US4104086A (en) 1977-08-15 1977-08-15 Method for forming isolated regions of silicon utilizing reactive ion etching
US824361 1977-08-15

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EP0000897A1 true EP0000897A1 (fr) 1979-03-07
EP0000897B1 EP0000897B1 (fr) 1981-12-23

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US (1) US4104086A (fr)
EP (1) EP0000897B1 (fr)
JP (1) JPS5432277A (fr)
CA (1) CA1097826A (fr)
DE (1) DE2861453D1 (fr)
IT (1) IT1112298B (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005728A1 (fr) * 1978-05-25 1979-12-12 International Business Machines Corporation Procédé de fabrication d'un transistor latéral PNP ou NPN à haut gain et transistor obtenu
EP0048175A2 (fr) * 1980-09-17 1982-03-24 Hitachi, Ltd. Dispositif semi-conducteur et procédé pour sa fabrication

Families Citing this family (148)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4264382A (en) * 1978-05-25 1981-04-28 International Business Machines Corporation Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions
US4276099A (en) * 1978-10-11 1981-06-30 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Fabrication of infra-red charge coupled devices
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
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US4104086A (en) 1978-08-01
IT7826393A0 (it) 1978-08-02
IT1112298B (it) 1986-01-13
DE2861453D1 (en) 1982-02-11
JPS5432277A (en) 1979-03-09
EP0000897B1 (fr) 1981-12-23
JPS6220696B2 (fr) 1987-05-08
CA1097826A (fr) 1981-03-17

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