DE69935100T2 - Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske - Google Patents

Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske Download PDF

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Publication number
DE69935100T2
DE69935100T2 DE69935100T DE69935100T DE69935100T2 DE 69935100 T2 DE69935100 T2 DE 69935100T2 DE 69935100 T DE69935100 T DE 69935100T DE 69935100 T DE69935100 T DE 69935100T DE 69935100 T2 DE69935100 T2 DE 69935100T2
Authority
DE
Germany
Prior art keywords
layer
etching
metallization
hard mask
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69935100T
Other languages
German (de)
English (en)
Other versions
DE69935100D1 (de
Inventor
Martin Gutsche
Peter Glen Allen Strobl
Stephan Wege
Eike Lueken
Georg Poughkeepsie Stojakovic
Bruno Spuler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Qimonda AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qimonda AG filed Critical Qimonda AG
Publication of DE69935100D1 publication Critical patent/DE69935100D1/de
Application granted granted Critical
Publication of DE69935100T2 publication Critical patent/DE69935100T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69935100T 1998-09-15 1999-08-12 Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske Expired - Lifetime DE69935100T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US153390 1998-09-15
US09/153,390 US6177353B1 (en) 1998-09-15 1998-09-15 Metallization etching techniques for reducing post-etch corrosion of metal lines

Publications (2)

Publication Number Publication Date
DE69935100D1 DE69935100D1 (de) 2007-03-29
DE69935100T2 true DE69935100T2 (de) 2007-12-13

Family

ID=22547020

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69935100T Expired - Lifetime DE69935100T2 (de) 1998-09-15 1999-08-12 Verfahren zur Ätzung einer Metallisierung mittels einer harten Maske

Country Status (7)

Country Link
US (1) US6177353B1 (enExample)
EP (1) EP0987745B1 (enExample)
JP (1) JP4690512B2 (enExample)
KR (1) KR100676995B1 (enExample)
CN (1) CN1146967C (enExample)
DE (1) DE69935100T2 (enExample)
TW (1) TW457583B (enExample)

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US10229837B2 (en) 2016-02-04 2019-03-12 Lam Research Corporation Control of directionality in atomic layer etching
US10727073B2 (en) 2016-02-04 2020-07-28 Lam Research Corporation Atomic layer etching 3D structures: Si and SiGe and Ge smoothness on horizontal and vertical surfaces
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JP6785101B2 (ja) * 2016-09-09 2020-11-18 東京エレクトロン株式会社 プラズマエッチング方法
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Also Published As

Publication number Publication date
CN1146967C (zh) 2004-04-21
US6177353B1 (en) 2001-01-23
DE69935100D1 (de) 2007-03-29
EP0987745A1 (en) 2000-03-22
EP0987745B1 (en) 2007-02-14
KR20000023166A (ko) 2000-04-25
JP4690512B2 (ja) 2011-06-01
TW457583B (en) 2001-10-01
JP2000323483A (ja) 2000-11-24
KR100676995B1 (ko) 2007-01-31
CN1270415A (zh) 2000-10-18

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8381 Inventor (new situation)

Inventor name: GUTSCHE, MARTIN, 84405 DORFEN, DE

Inventor name: STROBL, PETER, GLEN ALLEN, VA 23060, US

Inventor name: WEGE, STEPHAN, 01328 DRESDEN, DE

Inventor name: LUEKEN, EIKE, 01445 RADOBOUL, DE

Inventor name: STOJAKOVIC, GEORG, POUGHKEEPSIE, NY 12601, US

Inventor name: SPULER, BRUNO, 01478 WEIXDORF DRESDEN, DE

8364 No opposition during term of opposition