DE69807718T2 - Herstellungsverfahren für integrierte schaltkreise mit reduzierter dimension - Google Patents
Herstellungsverfahren für integrierte schaltkreise mit reduzierter dimensionInfo
- Publication number
- DE69807718T2 DE69807718T2 DE69807718T DE69807718T DE69807718T2 DE 69807718 T2 DE69807718 T2 DE 69807718T2 DE 69807718 T DE69807718 T DE 69807718T DE 69807718 T DE69807718 T DE 69807718T DE 69807718 T2 DE69807718 T2 DE 69807718T2
- Authority
- DE
- Germany
- Prior art keywords
- silicon
- given
- amorphized
- surface layer
- atoms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 67
- 229910052710 silicon Inorganic materials 0.000 claims description 66
- 239000010703 silicon Substances 0.000 claims description 66
- 239000010410 layer Substances 0.000 claims description 37
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 31
- 238000002844 melting Methods 0.000 claims description 24
- 230000008018 melting Effects 0.000 claims description 24
- 239000002344 surface layer Substances 0.000 claims description 23
- 238000005280 amorphization Methods 0.000 claims description 18
- 239000002019 doping agent Substances 0.000 claims description 17
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 230000005855 radiation Effects 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000007787 solid Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 15
- 239000007943 implant Substances 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 230000000295 complement effect Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 238000001816 cooling Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 3
- 238000002310 reflectometry Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 102000004310 Ion Channels Human genes 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/061—Gettering-armorphous layers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/792,107 US5908307A (en) | 1997-01-31 | 1997-01-31 | Fabrication method for reduced-dimension FET devices |
| PCT/US1998/001942 WO1998034268A2 (en) | 1997-01-31 | 1998-01-29 | Fabrication method for reduced-dimension integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69807718D1 DE69807718D1 (de) | 2002-10-10 |
| DE69807718T2 true DE69807718T2 (de) | 2003-07-31 |
Family
ID=25155818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69807718T Expired - Fee Related DE69807718T2 (de) | 1997-01-31 | 1998-01-29 | Herstellungsverfahren für integrierte schaltkreise mit reduzierter dimension |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5908307A (enExample) |
| EP (1) | EP1012879B1 (enExample) |
| JP (1) | JP2001509316A (enExample) |
| KR (1) | KR100511765B1 (enExample) |
| DE (1) | DE69807718T2 (enExample) |
| WO (1) | WO1998034268A2 (enExample) |
Families Citing this family (85)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6361951B1 (en) * | 1995-06-27 | 2002-03-26 | The University Of North Carolina At Chapel Hill | Electrochemical detection of nucleic acid hybridization |
| IT1289524B1 (it) * | 1996-12-24 | 1998-10-15 | Sgs Thomson Microelectronics | Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione |
| US6037640A (en) * | 1997-11-12 | 2000-03-14 | International Business Machines Corporation | Ultra-shallow semiconductor junction formation |
| US5956603A (en) * | 1998-08-27 | 1999-09-21 | Ultratech Stepper, Inc. | Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits |
| US6355543B1 (en) * | 1998-09-29 | 2002-03-12 | Advanced Micro Devices, Inc. | Laser annealing for forming shallow source/drain extension for MOS transistor |
| US6297115B1 (en) * | 1998-11-06 | 2001-10-02 | Advanced Micro Devices, Inc. | Cmos processs with low thermal budget |
| US6184112B1 (en) * | 1998-12-02 | 2001-02-06 | Advanced Micro Devices, Inc. | Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile |
| US6265291B1 (en) | 1999-01-04 | 2001-07-24 | Advanced Micro Devices, Inc. | Circuit fabrication method which optimizes source/drain contact resistance |
| US6771895B2 (en) * | 1999-01-06 | 2004-08-03 | Mattson Technology, Inc. | Heating device for heating semiconductor wafers in thermal processing chambers |
| US6395624B1 (en) * | 1999-02-22 | 2002-05-28 | International Business Machines Corporation | Method for forming implants in semiconductor fabrication |
| US6521501B1 (en) * | 1999-05-11 | 2003-02-18 | Advanced Micro Devices, Inc. | Method of forming a CMOS transistor having ultra shallow source and drain regions |
| US6265293B1 (en) | 1999-08-27 | 2001-07-24 | Advanced Micro Devices, Inc. | CMOS transistors fabricated in optimized RTA scheme |
| US6284630B1 (en) * | 1999-10-20 | 2001-09-04 | Advanced Micro Devices, Inc. | Method for fabrication of abrupt drain and source extensions for a field effect transistor |
| US6090651A (en) * | 1999-11-05 | 2000-07-18 | Lsi Logic Corporation | Depletion free polysilicon gate electrodes |
| US6586318B1 (en) * | 1999-12-28 | 2003-07-01 | Xerox Corporation | Thin phosphorus nitride film as an N-type doping source used in laser doping technology |
| US6645838B1 (en) | 2000-04-10 | 2003-11-11 | Ultratech Stepper, Inc. | Selective absorption process for forming an activated doped region in a semiconductor |
| US6570656B1 (en) | 2000-04-10 | 2003-05-27 | Ultratech Stepper, Inc. | Illumination fluence regulation system and method for use in thermal processing employed in the fabrication of reduced-dimension integrated circuits |
| US6380044B1 (en) * | 2000-04-12 | 2002-04-30 | Ultratech Stepper, Inc. | High-speed semiconductor transistor and selective absorption process forming same |
| US6294415B1 (en) * | 2000-04-26 | 2001-09-25 | United Microelectronics Corp. | Method of fabricating a MOS transistor |
| US6635588B1 (en) | 2000-06-12 | 2003-10-21 | Ultratech Stepper, Inc. | Method for laser thermal processing using thermally induced reflectivity switch |
| US6303476B1 (en) | 2000-06-12 | 2001-10-16 | Ultratech Stepper, Inc. | Thermally induced reflectivity switch for laser thermal processing |
| US6399450B1 (en) | 2000-07-05 | 2002-06-04 | Advanced Micro Devices, Inc. | Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions |
| US6335253B1 (en) | 2000-07-12 | 2002-01-01 | Chartered Semiconductor Manufacturing Ltd. | Method to form MOS transistors with shallow junctions using laser annealing |
| US6630386B1 (en) | 2000-07-18 | 2003-10-07 | Advanced Micro Devices, Inc | CMOS manufacturing process with self-amorphized source/drain junctions and extensions |
| JP2002050764A (ja) * | 2000-08-02 | 2002-02-15 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ、アレイ基板、液晶表示装置、有機ｅｌ表示装置およびその製造方法 |
| US6521502B1 (en) | 2000-08-07 | 2003-02-18 | Advanced Micro Devices, Inc. | Solid phase epitaxy activation process for source/drain junction extensions and halo regions |
| US6479821B1 (en) | 2000-09-11 | 2002-11-12 | Ultratech Stepper, Inc. | Thermally induced phase switch for laser thermal processing |
| US6365476B1 (en) | 2000-10-27 | 2002-04-02 | Ultratech Stepper, Inc. | Laser thermal process for fabricating field-effect transistors |
| US6594446B2 (en) | 2000-12-04 | 2003-07-15 | Vortek Industries Ltd. | Heat-treating methods and systems |
| US6970644B2 (en) * | 2000-12-21 | 2005-11-29 | Mattson Technology, Inc. | Heating configuration for use in thermal processing chambers |
| US7015422B2 (en) * | 2000-12-21 | 2006-03-21 | Mattson Technology, Inc. | System and process for heating semiconductor wafers by optimizing absorption of electromagnetic energy |
| US6495437B1 (en) | 2001-02-09 | 2002-12-17 | Advanced Micro Devices, Inc. | Low temperature process to locally form high-k gate dielectrics |
| US6403434B1 (en) | 2001-02-09 | 2002-06-11 | Advanced Micro Devices, Inc. | Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric |
| US6756277B1 (en) | 2001-02-09 | 2004-06-29 | Advanced Micro Devices, Inc. | Replacement gate process for transistors having elevated source and drain regions |
| US6551885B1 (en) | 2001-02-09 | 2003-04-22 | Advanced Micro Devices, Inc. | Low temperature process for a thin film transistor |
| US6787424B1 (en) | 2001-02-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Fully depleted SOI transistor with elevated source and drain |
| JP3904936B2 (ja) * | 2001-03-02 | 2007-04-11 | 富士通株式会社 | 半導体装置の製造方法 |
| US6387784B1 (en) | 2001-03-19 | 2002-05-14 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce polysilicon depletion in MOS transistors |
| US6885078B2 (en) * | 2001-11-09 | 2005-04-26 | Lsi Logic Corporation | Circuit isolation utilizing MeV implantation |
| US6555439B1 (en) * | 2001-12-18 | 2003-04-29 | Advanced Micro Devices, Inc. | Partial recrystallization of source/drain region before laser thermal annealing |
| CN101324470B (zh) | 2001-12-26 | 2011-03-30 | 加拿大马特森技术有限公司 | 测量温度和热处理的方法及系统 |
| KR100446622B1 (ko) * | 2002-01-10 | 2004-09-04 | 삼성전자주식회사 | 실리콘 광소자 및 이를 적용한 발광 디바이스 장치 |
| KR100940530B1 (ko) * | 2003-01-17 | 2010-02-10 | 삼성전자주식회사 | 실리콘 광소자 제조방법 및 이에 의해 제조된 실리콘광소자 및 이를 적용한 화상 입력 및/또는 출력장치 |
| US6723634B1 (en) * | 2002-03-14 | 2004-04-20 | Advanced Micro Devices, Inc. | Method of forming interconnects with improved barrier layer adhesion |
| JP4988202B2 (ja) | 2002-12-20 | 2012-08-01 | マトソン テクノロジー カナダ インコーポレイテッド | 工作物の支持及び熱処理の方法とシステム |
| JP4387355B2 (ja) | 2003-02-19 | 2009-12-16 | パナソニック株式会社 | 不純物導入方法 |
| US6803270B2 (en) * | 2003-02-21 | 2004-10-12 | International Business Machines Corporation | CMOS performance enhancement using localized voids and extended defects |
| US6844250B1 (en) | 2003-03-13 | 2005-01-18 | Ultratech, Inc. | Method and system for laser thermal processing of semiconductor devices |
| JP4589606B2 (ja) * | 2003-06-02 | 2010-12-01 | 住友重機械工業株式会社 | 半導体装置の製造方法 |
| JP4619951B2 (ja) | 2003-08-25 | 2011-01-26 | パナソニック株式会社 | 不純物導入層の形成方法 |
| JP4979234B2 (ja) | 2003-10-09 | 2012-07-18 | パナソニック株式会社 | 接合の形成方法およびこれを用いて形成された被処理物 |
| US7166528B2 (en) * | 2003-10-10 | 2007-01-23 | Applied Materials, Inc. | Methods of selective deposition of heavily doped epitaxial SiGe |
| WO2005059991A1 (en) | 2003-12-19 | 2005-06-30 | Mattson Technology Canada Inc. | Apparatuses and methods for suppressing thermally induced motion of a workpiece |
| US7112499B2 (en) * | 2004-01-16 | 2006-09-26 | Chartered Semiconductor Manufacturing Ltd. | Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal |
| US7312125B1 (en) | 2004-02-05 | 2007-12-25 | Advanced Micro Devices, Inc. | Fully depleted strained semiconductor on insulator transistor and method of making the same |
| US7078302B2 (en) * | 2004-02-23 | 2006-07-18 | Applied Materials, Inc. | Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal |
| KR20070011505A (ko) | 2004-05-14 | 2007-01-24 | 마쯔시다덴기산교 가부시키가이샤 | 반도체 장치의 제조방법 및 제조장치 |
| KR100612875B1 (ko) * | 2004-11-24 | 2006-08-14 | 삼성전자주식회사 | 실리콘 광소자 제조방법 및 이에 의해 제조된 실리콘광소자 및 이를 적용한 화상 입력 및/또는 출력장치 |
| KR20060059327A (ko) * | 2004-11-27 | 2006-06-01 | 삼성전자주식회사 | 실리콘 광소자 제조방법 및 이에 의해 제조된 실리콘광소자 및 이를 적용한 화상 입력 및/또는 출력장치 |
| US7235492B2 (en) | 2005-01-31 | 2007-06-26 | Applied Materials, Inc. | Low temperature etchant for treatment of silicon-containing surfaces |
| US7172954B2 (en) * | 2005-05-05 | 2007-02-06 | Infineon Technologies Ag | Implantation process in semiconductor fabrication |
| TW200713455A (en) * | 2005-09-20 | 2007-04-01 | Applied Materials Inc | Method to form a device on a SOI substrate |
| US7585763B2 (en) * | 2005-11-07 | 2009-09-08 | Samsung Electronics Co., Ltd. | Methods of fabricating integrated circuit devices using anti-reflective coating as implant blocking layer |
| CN101356632A (zh) * | 2006-01-13 | 2009-01-28 | 富士通株式会社 | 半导体器件的制造方法 |
| JP2008078166A (ja) * | 2006-09-19 | 2008-04-03 | Sony Corp | 薄膜半導体装置の製造方法および薄膜半導体装置 |
| WO2008058397A1 (en) | 2006-11-15 | 2008-05-22 | Mattson Technology Canada, Inc. | Systems and methods for supporting a workpiece during heat-treating |
| DE102007020261B4 (de) * | 2007-04-30 | 2009-07-16 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Erhöhung der Dotierstoffaktivierung unter Anwendung mehrerer sequenzieller fortschrittlicher Laser/Blitzlicht-Ausheizprozesse |
| US20090263944A1 (en) * | 2008-04-17 | 2009-10-22 | Albert Chin | Method for making low Vt gate-first light-reflective-layer covered dual metal-gates on high-k CMOSFETs |
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Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4617066A (en) * | 1984-11-26 | 1986-10-14 | Hughes Aircraft Company | Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing |
| US4904611A (en) * | 1987-09-18 | 1990-02-27 | Xerox Corporation | Formation of large grain polycrystalline films |
| US5342793A (en) * | 1990-02-20 | 1994-08-30 | Sgs-Thomson Microelectronics, S.R.L. | Process for obtaining multi-layer metallization of the back of a semiconductor substrate |
| US5147826A (en) * | 1990-08-06 | 1992-09-15 | The Pennsylvania Research Corporation | Low temperature crystallization and pattering of amorphous silicon films |
| JPH0521448A (ja) * | 1991-07-10 | 1993-01-29 | Sharp Corp | 半導体装置の製造方法 |
| KR970006723B1 (ko) * | 1993-09-07 | 1997-04-29 | 한국과학기술원 | 입자 크기가 큰 다결정 규소 박막의 제조방법 |
| KR970006262B1 (ko) * | 1994-02-04 | 1997-04-25 | 금성일렉트론 주식회사 | 도우핑된 디스포저블층(disposable layer)을 이용한 모스트랜지스터의 제조방법 |
| DE19505818A1 (de) * | 1995-02-09 | 1995-09-07 | Ulrich Prof Dr Mohr | Verfahren zum Dotieren von Halbleiterkristallen, insbesondere von Siliziumkristallen |
-
1997
- 1997-01-31 US US08/792,107 patent/US5908307A/en not_active Expired - Lifetime
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1998
- 1998-01-29 JP JP53316598A patent/JP2001509316A/ja not_active Ceased
- 1998-01-29 DE DE69807718T patent/DE69807718T2/de not_active Expired - Fee Related
- 1998-01-29 EP EP98909985A patent/EP1012879B1/en not_active Expired - Lifetime
- 1998-01-29 KR KR10-1999-7006907A patent/KR100511765B1/ko not_active Expired - Fee Related
- 1998-01-29 WO PCT/US1998/001942 patent/WO1998034268A2/en not_active Ceased
Also Published As
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|---|---|
| KR100511765B1 (ko) | 2005-09-05 |
| DE69807718D1 (de) | 2002-10-10 |
| EP1012879A2 (en) | 2000-06-28 |
| EP1012879A4 (en) | 2000-06-28 |
| WO1998034268A3 (en) | 1999-02-18 |
| KR20000070658A (ko) | 2000-11-25 |
| EP1012879B1 (en) | 2002-09-04 |
| WO1998034268A2 (en) | 1998-08-06 |
| JP2001509316A (ja) | 2001-07-10 |
| US5908307A (en) | 1999-06-01 |
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